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MPC5643L
MPC5643L Microcontroller Data Sheet
* High-performance e200z4d dual core - 32-bit Power ArchitectureTM Book E CPU - Core frequency as high as 120 MHz - Dual issue five-stage pipeline core - Variable Length Encoding (VLE) - Memory Management Unit (MMU) - 4 KB instruction cache with error detection code - Signal processing engine (SPE) * Memory available - 1 MB Flash memory with ECC - Built-in RWW capabilities for EEPROM emulation - As much as 128 KB on-chip RAM with ECC * SIL3/ASILD innovative safety concept: LockStep mode and Fail-safe protection - Sphere of replication (SoR) for key components (such as CPU core, DMA, crossbar switch) - Fault collection and control unit (FCCU) - Redundancy control and checker unit (RCCU) on outputs of the SoR connected to FCCU - Boot-time Built-In Self-Test for Memory (MBIST) and Logic (LBIST) triggered by hardware - Boot-time Built-In Self-Test for ADC and flash memory triggered by software - Replicated safety enhanced watchdog - Replicated junction temperature sensor - Non-maskable interrupt (NMI) - 16-region memory protection unit (MPU) - Clock monitoring units (CMU) - Power management unit (PMU) - Cyclic redundancy check (CRC) unit * Decoupled Parallel mode for high performance use of replicated cores * Nexus Class 3+ interface * Interrupts - Replicated 16-priority controller - Replicated 16-channel eDMA controller
LQFP 144 20 x 20 x 1.4 mm
257 MAPBGA 14 x 14 x 1.4 mm
* GPIOs individually programmable as input, output or special function * Three 6-channel general-purpose eTimer units * Two FlexPWM units - Four 16-bit channels per module * Communications interfaces - Two LINFlex channels - Three DSPI channels with automatic chip select generation - Two FlexCAN interfaces (2.0B Active) with 32 message objects - FlexRay module (V2.1) with dual channel, up to 64 message objects and speed as fast as 10 Mbit/s * Two 12-bit analog-to-digital converters (ADCs) - 16 input channels - Programmable cross triggering unit (CTU) to synchronize ADCs conversion with timer and PWM * Sine wave generator (D/A with low pass filter) * On-chip CAN/UART/FlexRay Bootstrap loader * Single 3.0 V to 3.6 V voltage supply * Ambient temperature range -40 C to 125 C * Junction temperature range -40 C to 150 C
This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. (c) Freescale Semiconductor, Inc., 2009. All rights reserved. Preliminary--Subject to Change Without Notice
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Freescale Semiconductor Data Sheet: Advance Information
Document Number: MPC5643L Rev. 3, 10/2009
Table of Contents
1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1.3 Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.3.1 High-performance e200z4d core . . . . . . . . . . . . .7 1.3.2 Crossbar switch (XBAR) . . . . . . . . . . . . . . . . . . .8 1.3.3 Memory Protection Unit (MPU) . . . . . . . . . . . . . .8 1.3.4 Enhanced Direct Memory Access (eDMA) . . . . .8 1.3.5 On-chip flash memory with ECC . . . . . . . . . . . . .9 1.3.6 On-chip SRAM with ECC. . . . . . . . . . . . . . . . . . .9 1.3.7 Platform flash controller . . . . . . . . . . . . . . . . . . . .9 1.3.8 Platform Static RAM Controller (SRAMC) . . . . .10 1.3.9 Memory subsystem access time . . . . . . . . . . . .10 1.3.10 Error Correction Status Module (ECSM) . . . . . .11 1.3.11 Peripheral bridge (PBRIDGE/AIPS-Lite) . . . . . .11 1.3.12 Interrupt Controller (INTC). . . . . . . . . . . . . . . . .11 1.3.13 System clocks and clock generation . . . . . . . . .12 1.3.14 Frequency-Modulated Phase-Locked Loop (FMPLL)12 1.3.15 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . .12 1.3.16 Internal Reference Clock (RC) oscillator . . . . . .13 1.3.17 Clock, reset, power, mode and test control module13 1.3.18 Periodic Interrupt Timer Module (PIT) . . . . . . . .13 1.3.19 System Timer Module (STM). . . . . . . . . . . . . . .13 1.3.20 Software Watchdog Timer (SWT) . . . . . . . . . . .13 1.3.21 Fault Collection and Control Unit (FCCU) . . . . .14 1.3.22 System Integration Unit Lite (SIUL) . . . . . . . . . .14 1.3.23 Non-Maskable Interrupt (NMI) . . . . . . . . . . . . . .14 1.3.24 Boot Assist Module (BAM). . . . . . . . . . . . . . . . .14 1.3.25 System Status and Configuration Module (SSCM) 15 1.3.26 FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 1.3.27 FlexRay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1.3.28 Serial communication interface module (LINFlex)16 1.3.29 Serial Peripheral Interface module (DSPI). . . . .17 1.3.30 FlexPWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.3.31 eTimer module. . . . . . . . . . . . . . . . . . . . . . . . . .18 1.3.32 Sine Wave Generator (SWG) . . . . . . . . . . . . . .18 1.3.33 Analog-to-Digital Converter module (ADC) . . . .19 1.3.34 Cross Triggering Unit (CTU) . . . . . . . . . . . . . . .19 1.3.35 Cyclic Redundancy Checker (CRC) Unit . . . . . .20 1.3.36 Redundancy Control and Checker Unit (RCCU)20 1.3.37 Junction temperature sensor . . . . . . . . . . . . . . .20 1.3.38 Nexus Port Controller (NPC) . . . . . . . . . . . . . . .20 2 1.3.39 IEEE 1149.1 JTAG Controller (JTAGC) . . . . . . 21 1.3.40 Voltage regulator / Power Management Unit (PMU)22 1.3.41 Built-In Self-Test (BIST) capability . . . . . . . . . . 22 Package pinouts and signal descriptions . . . . . . . . . . . . . . . 22 2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2.1 Concatenated pins . . . . . . . . . . . . . . . . . . . . . . 25 2.2.2 Power supply and reference voltage pins. . . . . 38 2.2.3 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.2.4 Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . 58 3.3 Recommended operating conditions . . . . . . . . . . . . . . 59 3.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 60 3.4.1 General notes for specifications at maximum junction temperature. . . . . . . . . . . . . . . . . . . . . 61 3.5 Electromagnetic Interference (EMI) characteristics . . . 63 3.6 Electrostatic discharge (ESD) characteristics . . . . . . . 63 3.7 Static latch-up (LU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.8 Voltage regulator electrical characteristics . . . . . . . . . 64 3.9 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . 66 3.10 Temperature sensor electrical characteristics . . . . . . . 67 3.11 Main oscillator electrical characteristics . . . . . . . . . . . 68 3.12 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 69 3.13 16 MHz RC oscillator electrical characteristics . . . . . . 71 3.14 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . 72 3.14.1 Input Impedance and ADC Accuracy . . . . . . . . 72 3.15 Flash memory electrical characteristics . . . . . . . . . . . 77 3.16 AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 3.16.1 Pad AC specifications. . . . . . . . . . . . . . . . . . . . 78 3.17 AC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . 79 3.17.1 RESET pin characteristics . . . . . . . . . . . . . . . . 79 3.17.2 IEEE 1149.1 interface timing . . . . . . . . . . . . . . 80 3.17.3 Nexus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.17.4 External interrupt timing (IRQ pin) . . . . . . . . . . 84 3.17.5 FlexCAN timing . . . . . . . . . . . . . . . . . . . . . . . . 85 3.17.6 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Package characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . 92 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
3
4 5 6
MPC5643L Microcontroller Data Sheet, Rev. 3 2 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Overview
1
Overview
This document provides electrical specifications, pin assignments, and package diagrams for the MPC5643L series of microcontroller units (MCUs). For functional characteristics, refer to the MPC5643L Microcontroller Reference Manual. For use of the MPC5643Lin a fail-safe system according to safety standard IEC 61508, refer to the MPC5643LSafety Application Guide. The MPC5643L series microcontrollers are system-on-chip devices that are built on Power ArchitectureTM technology and: * * * * Are 100% user-mode compatible with the classic Power Architecture instruction set Contain enhancements that improve the architecture's fit in embedded applications Include additional instruction support for digital signal processing (DSP) Integrate technologies such as an enhanced time processor unit, enhanced queued analog-to-digital converter, Controller Area Network, and an enhanced modular input-output system
This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the devices. The MPC5643L family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. It belongs to an expanding range of automotive-focused products designed to address electrical hydraulic power steering (EHPS), electric power steering (EPS) and airbag applications. The advanced and cost-efficient host processor core of the MPC5643L automotive controller family complies with the Power Architecture embedded category, which is 100 percent user-mode compatible with the original PowerPC user instruction set architecture (UISA). It operates at speeds as high as 120 MHz and offers high performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations.
1.1
Device comparison
Table 1. MPC5643L device summary
Feature CPU Type Architecture Execution speed DMIPS intrinsic performance SIMD (DSP + FPU) MMU Instruction set PPC Instruction set VLE Instruction cache MPU-16 regions Semaphore unit (SEMA4) Buses Core bus Internal periphery bus Crossbar Master x slave ports MPC5643L 2 x e200z4 (in lock-step or decoupled operation) Harvard 0 - 120 MHz (+2% FM) > 240 MIPS Yes 16 entry Yes Yes 4 KB, EDC Yes, replicated module Yes AHB, 32-bit address, 64-bit data 32-bit address, 32-bit data Lock Step Mode: 4 x 3 Decoupled Parallel Mode: 6 x 3
MPC5643L Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 3
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Overview
Table 1. MPC5643L device summary (continued)
Feature Memory Code/data flash Static RAM Modules Interrupt controller Periodic Interrupt Timer (PIT) System timer module Software watchdog timer eDMA FlexRay FlexCAN LINFlex (UART and LIN) Clock out Fault control & collection unit (FCCU) Cross triggering unit (CTU) eTimer FlexPWM ADC Sine-wave generator DSPI Cyclic redundancy checker (CRC) unit Junction temperature sensor with analog comparator Digital I/Os Supply Device power supply MPC5643L 1 MB, ECC, RWW 128 KB, ECC 16 interrupt levels, replicated module 1 x 4 channels 1 x 4 channels, replicated module Yes, replicated module 16 channels, replicated module 1 x 64 message buffer, dual channel 2 x 32 message buffer 2 Yes Yes Yes 3 x 6 channels1 2 Module 4 x (2 + 1) channels2 2 x 12-bit ADC, 16 channels per ADC (3 internal, 4 shared and 9 external) 32 point 3 x DSPI as many as 8 chip selects Yes Yes, replicated module 16 3.3 V with integrated bypassable ballast transistor External ballast transistor not needed for bare die 3.0 V - 3.6 V and 4.5 V - 5.5 V 2 16 MHz 4 - 40 MHz Level 3+
Analog reference voltage Clocking Frequency-modulated phase-locked loop (FMPLL) Internal RC oscillator External crystal oscillator Debug Nexus
MPC5643L Microcontroller Data Sheet, Rev. 3 4 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Overview
Table 1. MPC5643L device summary (continued)
Feature Packages Known Good Die (KGD) LQFP MAPBGA Temperature Temperature range (junction) Ambient temperature range using external ballast transistor (LQFP) Ambient temperature range using external ballast transistor (BGA) NOTES: 1 The third eTimer is available only in the BGA package. 2 The second FlexPWM module is available only in the BGA package. MPC5643L Yes 144 pins 257 MAPBGA -40 to 150 C -40 to 125 C TBD
MPC5643L Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Overview
1.2
Block diagram
PMU SWT ECSM STM INTC SEMA4 DMA SPE VLE MMU I-CACHE FlexRay RC PMU SWT SPE VLE MMU I-CACHE ECSM STM INTC SEMA4 DMA
Figure 1 shows a top-level block diagram of the MPC5643L device.
e200z4
JTAG Nexus
e200z4
Crossbar Switch Memory Protection Unit ECC logic for SRAM
Crossbar Switch Memory Protection Unit ECC logic for SRAM
AIPS Bridge
RC
RC
AIPS Bridge
TSENS
Flash memory ECC bits + logic RC
Secondary PLL
SRAM ECC bits
T-Sens
ADC AIPS BAM CMU CRC CTU DMA DSPI ECC ECSM FCCU FlexCAN FMPLL INTC IRCOSC
- Analog-to-Digital Converter - AHB to IP Slave Bus bridge - Boot Assist Module - Clock Monitoring Unit - Cyclic Redundancy Check unit - Cross Triggering Unit - Direct Memory Access controller - Serial Peripherals Interface - Error Correction Code - Error Correction Status Module - Fault Collection and Control Unit - Controller Area Network controller - Frequency Modulated Phase Locked Loop - Interrupt Controller - Internal RC Oscillator
JTAG MC PIT PMU RC RTC SEMA4 SIUL SSCM STM SWG SWT TSENS XOSC
- Joint Test Action Group interface - Mode Entry, Clock, Reset, & Power - Periodic Interrupt Timer - Power Management Unit - Redundancy Checker - Real Time Clock - Semaphore Unit - System Integration Unit Lite - System Status and Configuration Module - System Timer Module - Sine Wave Generator - Software Watchdog Timer - Temperature Sensor - Crystal Oscillator
Figure 1. MPC5643L block diagram
MPC5643L Microcontroller Data Sheet, Rev. 3 6 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
IRCOSC
FMPLL
SSCM
CMU
CMU
CMU
BAM
CRC FlexPWM FlexPWM FlexCAN FlexCAN LINFlex LINFlex eTimer eTimer eTimer DSPI DSPI DSPI CTU
WakeUp
XOSC
SIUL
FCCU
ADC
ADC
PIT SWG
MC
Overview
1.3
1.3.1
* *
Feature details
High-performance e200z4d core
Two independent execution units, both supporting fixed-point and floating-point operations Dual issue 32-bit Power ArchitectureTM (Book E) compliant -- Five-stage pipeline (IF, DEC, EX1, EX2, WB) -- In-order execution and instruction retirement Full support for Power Architecture instruction set and Variable Length Encoding (VLE) -- Mix of classic 32-bit and 16-bit instruction allowed -- Optimization of code size possible Thirty-two 64-bit general purpose registers (GPRs) Harvard bus (32-bit address, 64-bit data) -- I-Bus interface capable of one outstanding transaction plus one piped with no wait-on-data return -- D-Bus interface capable of two transactions outstanding to fill AHB pipe I-cache and I-cache controller -- 4 KB, 256-bit cache line (programmable for 2- or 4-way) No data cache 16-entry MMU 8-entry branch table buffer Branch look-ahead instruction buffer to accelerate branching Dedicated branch address calculator Three cycles worst case for missed branch Load/store unit -- Fully pipelined -- Single-cycle load latency -- Big- and little-endian modes supported -- Misaligned access support -- Single stall cycle on load to use Single-cycle throughput (two-cycle latency) integer 32 x 32 multiplication 4 - 14 cycles integer 32 x 32 division (average division on various benchmark of nine cycles) Single precision floating-point unit -- 1 cycle throughput (2-cycle latency) floating-point 32 x 32 multiplication -- Target nine cycles (worst case acceptable is 12 cycles) throughput floating-point 32 x 32 division -- Special square root and min/max function implemented Signal processing support: APU-SPE 1.1 -- Support for vectorized mode: as many as two floating-point instructions per clock Vectored interrupt support Reservation instruction to support read-modify-write constructs Extensive system development and tracing support via Nexus debug port
The e200z4d Power ArchitectureTM core provides the following features:
*
* *
* * * * * * * *
* * *
* * * *
MPC5643L Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 7
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Overview
1.3.2
Crossbar switch (XBAR)
The XBAR multi-port crossbar switch supports simultaneous connections between four master ports and three slave ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus width. The crossbar allows four concurrent transactions to occur from any master port to any slave port, although one of those transfers must be an instruction fetch from internal flash memory. If a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher priority master and grants it ownership of the slave port. All other masters requesting that slave port are stalled until the higher priority master completes its transactions. The crossbar provides the following features: * Four masters and three slaves supported per each replicated crossbar -- Masters allocation for each crossbar: e200z4d core with two independent bus interface units (BIU) for I and D access (two masters), one DMA, one FlexRay -- Slaves allocation for each crossbar: a redundant flash-memory controller with two slave ports to guarantee maximum flexibility to handle Instruction and Data array, one redundant SRAM controller with one slave port each and one redundant peripheral bus bridge 32-bit address bus and 64-bit data bus Programmable arbitration priority -- Requesting masters can be treated with equal priority and are granted access to a slave port in round-robin method, based upon the ID of the last master to be granted access or a priority order can be assigned by software at application run time Temporary dynamic priority elevation of masters
* *
*
The XBAR is replicated for each processor.
1.3.3
Memory Protection Unit (MPU)
The Memory Protection Unit splits the physical memory into 16 different regions. Each master (DMA, FlexRay, CPU) can be assigned different access rights to each region. * * 16-region MPU with concurrent checks against each master access 32-byte granularity for protected address region
The memory protection unit is replicated for each processor.
1.3.4
Enhanced Direct Memory Access (eDMA)
The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data movements via 16 programmable channels, with minimal intervention from the host processor. The hardware microarchitecture includes a DMA engine which performs source and destination address calculations, and the actual data movement operations, along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels. This implementation is used to minimize the overall block size. The eDMA module provides the following features: * * * * * * * * 16 channels supporting 8-, 16-, and 32-bit value single or block transfers Support variable sized queues and circular buffered queue Source and destination address registers independently configured to post-increment or stay constant Support major and minor loop offset Support minor and major loop done signals DMA task initiated either by hardware requestor or by software Each DMA task can optionally generate an interrupt at completion and retirement of the task Signal to indicate closure of last minor loop
MPC5643L Microcontroller Data Sheet, Rev. 3 8 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Overview
*
Transfer control descriptors mapped inside the SRAM
The eDMA controller is replicated for each processor.
1.3.5
On-chip flash memory with ECC
This device includes programmable, non-volatile flash memory. The non-volatile memory (NVM) can be used for instruction storage or data storage, or both. The flash memory module interfaces with the system bus through a dedicated flash memory array controller. It supports a 64-bit data bus width at the system bus port, and a 128-bit read data interface to flash memory. The module contains four 128-bit prefetch buffers. Prefetch buffer hits allow no-wait responses. Buffer misses incur a 3 wait state response at 120 MHz. The flash memory module provides the following features * * * * * * * * 1 MB of flash memory in unique multi-partitioned hard macro Sectorization: 16 KB + 2 x 48 KB + 16 KB + 2 x 64 KB + 2 x 128 KB + 2 x 256 KB EEPROM emulation (in software) within same module but on different partition 16 KB Test and 16 KB shadow sector for test, censorship device and user option bits 3 wait states at 120 MHz Flash line 128-bit wide with 8-bit ECC on 64-bit word (total 144 bits) Accessed via a 64-bit wide bus for write and a 128-bit wide array for read operations 1-bit error correction, 2-bit error detection
1.3.6
On-chip SRAM with ECC
The MPC5643L SRAM provides a general-purpose single port memory. ECC handling is done on a 32-bit boundary for data and it is extended to the address to have the highest possible diagnostic coverage including the array internal address decoder. The SRAM module provides the following features: * * * System SRAM: 128 KB ECC on 32-bit word (syndrome of 7 bits) -- ECC covers SRAM bus address 1-bit error correction, 2-bit error detection
1.3.7
* * *
Platform flash controller
Single AHB port interface supports a 64-bit data bus. All AHB aligned and unaligned reads within the 32-bit container are supported. Only aligned word writes are supported. Array interfaces support a 128-bit read data bus and a 64-bit write data bus for each bank. Code flash (bank0) interface provides configurable read buffering and page prefetch support. -- Four page-read buffers (each 128 bits wide) and a prefetch controller support speculative reading and optimized flash access. Single-cycle read responses (zero AHB data-phase wait states) for hits in the buffers. The buffers implement a least-recently-used replacement algorithm to maximize performance. Data flash (bank1) interface includes a 128-bit register to temporarily hold a single flash page. This logic supports single-cycle read responses (0 AHB data-phase wait states) for accesses that hit in the holding register. -- No prefetch support is provided for this bank.
The following list summarizes the key features of the flash controller:
* *
MPC5643L Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 9
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Overview
* * * * *
Programmable response for read-while-write sequences including support for stall-while-write, optional stall notification interrupt, optional flash operation abort, and optional abort notification interrupt. Separate and independent configurable access timing (on a per bank basis) to support use across a wide range of platforms and frequencies. Support of address-based read access timing for emulation of other memory types. Support for reporting of single- and multi-bit error events. Typical operating configuration loaded into programming model by system reset.
The platform flash controller is replicated for each processor.
1.3.8
Platform Static RAM Controller (SRAMC)
The SRAMC module is the platform RAM array controller, with integrated error detection and correction. The main features of the SRAMC provide connectivity for the following interfaces: * * * * * * XBAR Slave Port (64-bit data path) ECSM (ECC Error Reporting, error injection and configuration) RAM array ECC encoding (32-bit boundary for data and complete address bus) ECC decoding (32-bit boundary and entire address) Address translation from the AHB protocol on the XBAR to the RAM Array
The following functions are implemented:
The platform RAM controller is replicated for each processor.
1.3.9
Memory subsystem access time
Every memory access the CPU performs requires at least one system clock cycle for the data phase of the access. Slower memories or peripherals may require additional data phase wait states. Additional data phase wait states may also occur if the slave being accessed is not parked on the requesting master in the crossbar. Table 2 shows the number of additional data phase wait states required for a range of memory accesses. Table 2. Platform memory access time summary
AHB Transfer e200z4d Instruction Fetch e200z4d Instruction Fetch e200z4d Data Read e200z4d Data Write e200z4d Data Write e200z4d Data Write e200z4d Data Flash Read e200z4d Data Flash Read Data Phase Wait States TBD1 TBD TBD TBD TBD TBD TBD TBD Description Flash prefetch buffer hit (page hit) Flash prefetch buffer miss (at 120 MHz) (based on 4-cycle random flash array access time) RAM read RAM 32-bit write RAM 64-bit write (executed as 2 x 32-bit writes) RAM 8-,16-bit write (Read-modify-Write for ECC) Flash prefetch buffer hit (page hit) Flash prefetch buffer miss (includes 1-cycle of program flash controller arbitration)
MPC5643L Microcontroller Data Sheet, Rev. 3 10 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Overview
Table 2. Platform memory access time summary (continued)
AHB Transfer e200z4d Peripheral Read e200z4d Peripheral Write NOTES: 1 To be determined Data Phase Wait States TBD TBD Peripheral Bridge read Peripheral Bridge write Description
1.3.10
Error Correction Status Module (ECSM)
The ECSM on this device manages the ECC configuration and reporting for the platform memories (flash memory and SRAM). It does not implement the actual ECC calculation. A detected error (double error for flash memory or SRAM) is also reported to the FCCU. The following errors and indications are reported into the ECSM dedicated registers: * * * * ECC error status and configuration for flash memory and SRAM ECC error reporting for flash memory ECC error reporting for SRAM ECC error injection for RAM
1.3.11
* * * * * *
Peripheral bridge (PBRIDGE/AIPS-Lite)
The peripheral bridge (referred to as PBRIDGE or AIPS-Lite throughout this document) implements the following features: Duplicated periphery Protocol translator bridge from AMBA to internal periphery interface (IPI) Master access right per peripheral (per master: read access enable; write access enable) Write buffering for peripherals Checker applied on AIPS-Lite output toward periphery Byte endianess swap capability
1.3.12
Interrupt Controller (INTC)
The INTC (interrupt controller) provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard real-time systems. For high-priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of interrupt request, the priority of each interrupt request is software configurable. The INTC supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the resource can not preempt each other. The INTC provides the following features: * * * * Duplicated periphery Unique 9-bit vector per interrupt source 16 priority levels with fixed hardware arbitration within priority levels for each interrupt source Priority elevation for shared resource
The INTC is replicated for each processor.
MPC5643L Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Overview
1.3.13
* * * * * * * *
System clocks and clock generation
The following list summarizes the system clock and clock generation on this device: Lock status continuously monitored by lock detect circuitry Loss-of-clock (LOC) detection for reference and feedback clocks On-chip loop filter (for improved electromagnetic interference performance and fewer external components required) Programmable output clock divider of system clock (/1, /2, /4, /8) FlexPWM module and as many as three eTimer modules running on an auxiliary clock independent from system clock (with max frequency 120 MHz) On-chip crystal oscillator with automatic level control Dedicated internal 16 MHz internal RC oscillator for rapid start-up -- Supports automated frequency trimming by hardware during device startup and by user application Auxiliary clock domain for motor control periphery (FlexPWM, eTimer, CTU, ADC, and SWG)
1.3.14
Frequency-Modulated Phase-Locked Loop (FMPLL)
Two FMPLLs are available on each device. Each FMPLL allows the user to generate high speed system clocks starting from a minimum reference of 4 MHz input clock. Further, the FMPLL supports programmable frequency modulation of the system clock. The PLL multiplication factor, output clock divider ratio are all software configurable. The FMPLLs have the following major features: * * * Input frequency: 4-40 MHz continuous range (limited by the crystal oscillator) Voltage controlled oscillator (VCO) range: 256-512 MHz Frequency modulation via software control to reduce and control emission peaks -- Modulation depth 2% if centered or 0% to -4% if downshifted via software control register -- Modulation frequency: triangular modulation with 25 kHz nominal rate Option to switch modulation on and off via software interface Reduced frequency divider (RFD) for reduced frequency operation without re-lock Three modes of operation -- Bypass mode -- Normal PLL mode with crystal reference (default) -- Normal PLL mode with external reference Lock monitor circuitry with lock status Loss-of-lock detection for reference and feedback clocks Self-clocked mode (SCM) operation On-chip loop filter Auxiliary FMPLL -- Used for FlexRay due to precise symbol rate requirement by the protocol -- Used for motor control periphery and connected IP (A/D digital interface CTU) to allow independent frequencies of operation for PWM and timers and jitter-free control -- Option to enable/disable modulation to avoid protocol violation on jitter and/or potential unadjusted error in electric motor control loop -- Allows to run motor control periphery at different (precisely lower, equal or higher as required) frequency than the system to ensure higher resolution
* * *
* * * * *
1.3.15
Main oscillator
The main oscillator provides these features:
MPC5643L Microcontroller Data Sheet, Rev. 3 12 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Overview
* * * *
Input frequency range 4-40 MHz Crystal input mode External reference clock (3.3 V) input mode PLL reference
1.3.16
Internal Reference Clock (RC) oscillator
The architecture uses constant current charging of a capacitor. The voltage at the capacitor is compared to the stable bandgap reference voltage. The RC oscillator is the device safe clock. The RC oscillator provides these features: * * * * Nominal frequency 16 MHz 5% variation over voltage and temperature after process trim Clock output of the RC oscillator serves as system clock source in case loss of lock or loss of clock is detected by the PLL RC oscillator is used as the default system clock during startup and can be used as back-up input source of PLL(s) in case XOSC fails
1.3.17
* * * *
Clock, reset, power, mode and test control module
The Clock, Reset, Power, Mode and Test control module has the following features: Clock gating and clock distribution control Halt, stop mode control Flexible configurable System and auxiliary clock dividers Various execution modes -- Reset, Idle, Test, Safe -- Various RUN modes with software selectable powered modules -- No stand-by mode implemented (no internal switchable power domains)
1.3.18
* * * *
Periodic Interrupt Timer Module (PIT)
The PIT module implements the following features: Four general purpose interrupt timers 32-bit counter resolution 32-bit counter for real time interrupt, clocked from main external oscillator Can be used for software tick or DMA trigger operation
1.3.19
* *
System Timer Module (STM)
The STM implements the following features: Up-counter with four output compare registers OS task protection and hardware tick implementation per AutoSar requirement
The STM is replicated for each processor.
1.3.20
Software Watchdog Timer (SWT)
This module implements the following features:
MPC5643L Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 13
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Overview
* * * * *
Fault tolerant output Safe internal RC oscillator as reference clock Windowed watchdog Program flow control monitor with 16-bit pseudorandom key generation Allows a high level of safety (SIL3 monitor)
The SWT module is replicated for each processor.
1.3.21
* * * *
Fault Collection and Control Unit (FCCU)
The FCCU module has the following features: Redundant collection of hardware checker results Redundant collection of error information and latch of faults from critical modules on the device Collection of self-test results Configurable and graded fault control -- Internal reactions (no internal reaction, IRQ, Functional Reset, Destructive Reset, or Safe mode entered) -- External reaction (failure is reported to the external/surrounding system via configurable output pins)
1.3.22
System Integration Unit Lite (SIUL)
The SIUL controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O (GPIO), internal peripheral multiplexing, and the system reset operation. The reset configuration block contains the external pin boot configuration logic. The pad configuration block controls the static electrical characteristics of I/O pins. The GPIO block provides uniform and discrete input/output control of the I/O pins of the MCU. The SIU provides the following features: * Centralized pad control on per pin basis -- Pin function selection -- Configurable weak pull-up/down -- Configurable slew rate control (slow/medium/fast) -- Hysteresis on GPIO pins -- Configurable automatic safe mode pad control Input filtering for external interrupts
*
1.3.23
Non-Maskable Interrupt (NMI)
The non-maskable interrupt with de-glitching filter supports high priority core exceptions.
1.3.24
Boot Assist Module (BAM)
The BAM is a block of read-only memory with hard-coded content. The BAM program is executed only if serial booting mode is selected via boot configuration pins. The BAM provides the following features: * * * * Enables booting via serial mode (FlexCAN or LINFlex-UART) Supports programmable 64-bit password protection for serial boot mode Supports serial bootloading of either classic PowerPC Book E code (default) or Freescale VLE code Automatic switch to serial boot mode if internal flash memory is blank or invalid
MPC5643L Microcontroller Data Sheet, Rev. 3 14 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Overview
1.3.25
* * * * *
System Status and Configuration Module (SSCM)
The SSCM on this device features the following: System configuration and status Debug port status and debug port enable Multiple boot code starting locations out of reset through implementation of search for valid Reset Configuration Half Word Sets up the MMU to allow user boot code to execute as either classic PowerPC Book E code (default) or as Freescale VLE code out of flash memory Triggering of device self-tests during reset phase of device boot
1.3.26
FlexCAN
The FlexCAN module is a communication controller implementing the CAN protocol according to Bosch Specification version 2.0B. The CAN protocol was designed to be used primarily as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness and required bandwidth. The FlexCAN module provides the following features: * Full implementation of the CAN protocol specification, version 2.0B -- Standard data and remote frames -- Extended data and remote frames -- 0 to 8 bytes data length -- Programmable bit rate as fast as 1Mbit/s 32 message buffers of 0 to 8 bytes data length Each message buffer configurable as receive or transmit buffer, all supporting standard and extended messages Programmable loop-back mode supporting self-test operation Three programmable mask registers Programmable transmit-first scheme: lowest ID or lowest buffer number Time stamp based on 16-bit free-running timer Global network time, synchronized by a specific message Maskable interrupts Independent of the transmission medium (an external transceiver is assumed) High immunity to EMI Short latency time due to an arbitration scheme for high-priority messages Transmit features -- Supports configuration of multiple mailboxes to form message queues of scalable depth -- Arbitration scheme according to message ID or message buffer number -- Internal arbitration to guarantee no inner or outer priority inversion -- Transmit abort procedure and notification Receive features -- Individual programmable filters for each mailbox -- Eight mailboxes configurable as a 6-entry receive FIFO -- Eight programmable acceptance filters for receive FIFO Programmable clock source -- System clock -- Direct oscillator clock to avoid PLL jitter
* * * * * * * * * * * *
*
*
MPC5643L Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 15
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Overview
1.3.27
* * * * * * * * *
FlexRay
The FlexRay module provides the following features: Full implementation of FlexRay Protocol Specification 2.1 64 configurable message buffers can be handled Dual channel or single channel mode of operation, each as fast as 10 Mbit/s data rate Message buffers configurable as transmit, receive, or receive FIFO Message buffer size configurable Message filtering for all message buffers based on Frame ID, cycle count, and message ID Programmable acceptance filters for receive FIFO message buffers Memory mapped message buffers (shared using the MPU) ECC to cover lookup table and data SRAM
1.3.28
* * * *
Serial communication interface module (LINFlex)
The LINFlex on this device features the following: Supports LIN Master mode, LIN Slave mode and UART mode LIN state machine compliant to LIN1.3, 2.0, and 2.1 specifications Manages LIN frame transmission and reception without CPU intervention LIN features -- Autonomous LIN frame handling -- Message buffer to store as many as 8 data bytes -- Supports messages as long as 64 bytes -- Detection and flagging of LIN errors (Sync field, delimiter, ID parity, bit framing, checksum and Time-out errors) -- Classic or extended checksum calculation -- Configurable break duration of up to 36-bit times -- Programmable baud rate prescalers (13-bit mantissa, 4-bit fractional) -- Diagnostic features (Loop back, LIN bus stuck dominant detection) -- Interrupt driven operation with 16 interrupt sources LIN slave mode features -- Autonomous LIN header handling -- Autonomous LIN response handling UART mode -- Full-duplex operation -- Standard non return-to-zero (NRZ) mark/space format -- Data buffers with 4-byte receive, 4-byte transmit -- Configurable word length (8-bit, 9-bit, or 16-bit words) -- Configurable parity scheme: none, odd, even, always 0 -- Speed as fast as 2 Mbit/s -- Error detection and flagging (Parity, Noise and Framing errors) -- Interrupt driven operation with four interrupt sources -- Separate transmitter and receiver CPU interrupt sources -- 16-bit programmable baud-rate modulus counter and 16-bit fractional -- Two receiver wake-up methods Support for DMA enabled transfers
*
*
*
MPC5643L Microcontroller Data Sheet, Rev. 3 16 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Overview
1.3.29
Serial Peripheral Interface module (DSPI)
The serial peripheral interface (DSPI) block provides a synchronous serial interface for communication between the MPC5643L and external devices. A DSPI module provides these features: * * * * * * * * * * * * * Full duplex, synchronous transfers Master or slave operation Programmable master bit rates Programmable clock polarity and phase End-of-transmission interrupt flag Programmable transfer baud rate Programmable data frames from 4 to 16 bits As many as eight chip select lines available, depending on package and pin multiplexing Four clock and transfer attributes registers Chip select strobe available as alternate function on one of the chip select pins for de-glitching FIFOs for buffering as many as five transfers on the transmit and receive side Queueing operation possible through use of the eDMA General purpose I/O functionality on pins when not used for SPI
1.3.30
FlexPWM
The pulse width modulator module (FlexPWM) contains four PWM channels, each of which is configured to control a single half-bridge power stage. Two modules are instantiated on the 257 MAPBGA device; on the 144 LQFP package, only one module is present. Additionally, four fault input channels are provided per FlexPWM module. This PWM is capable of controlling most motor types, including: * * * * * * * * * * * * * AC induction motors (ACIM) Permanent Magnet AC motors (PMAC) Brushless (BLDC) and brush DC motors (BDC) Switched (SRM) and variable reluctance motors (VRM) Stepper motors 16 bits of resolution for center, edge aligned, and asymmetrical PWMs Maximum operating frequency as high as 120 MHz -- Clock source not modulated and independent from system clock (generated via auxiliary PLL) Fine granularity control for enhanced resolution of the PWM period PWM outputs can operate as complementary pairs or independent channels Ability to accept signed numbers for PWM generation Independent control of both edges of each PWM output Synchronization to external hardware or other PWM supported Double buffered PWM registers -- Integral reload rates from 1 to 16 -- Half cycle reload capability Multiple ADC trigger events can be generated per PWM cycle via hardware Fault inputs can be assigned to control multiple PWM outputs Programmable filters for fault inputs
A FlexPWM module implements the following features:
* * *
MPC5643L Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Overview
* * * * * * * * * *
*
Independently programmable PWM output polarity Independent top and bottom deadtime insertion Each complementary pair can operate with its own PWM frequency and deadtime values Individual software control for each PWM output All outputs can be forced to a value simultaneously PWMX pin can optionally output a third signal from each channel Channels not used for PWM generation can be used for buffered output compare functions Channels not used for PWM generation can be used for input capture functions Enhanced dual edge capture functionality Option to supply the source for each complementary PWM signal pair from any of the following: -- External digital pin -- Internal timer channel -- External ADC input, taking into account values set in ADC high and low limit registers DMA support
1.3.31
eTimer module
The Leopard provides three eTimer modules on the 257 MAPBGA device, and two eTimer modules on the 144 LQFP package. Six 16-bit general purpose up/down timer/counters per module are implemented with the following features: * * Maximum clock frequency 120 MHz Individual channel capability -- Input capture trigger -- Output compare -- Double buffer (to capture rising edge and falling edge) -- Separate prescaler for each counter -- Selectable clock source -- 0-100% pulse measurement -- Rotation direction flag (Quad decoder mode) Maximum count rate -- Equals peripheral clock divided by 2 for external event counting -- Equals peripheral clock for internal clock counting Cascadeable counters Programmable count modulo Quadrature decode capabilities Counters can share available input pins Count once or repeatedly Preloadable counters Pins available as GPIO when timer functionality not in use DMA support
*
* * * * * * * *
1.3.32
Sine Wave Generator (SWG)
A customized digital-to-analog converter is available to generate a sine wave based on 32 stored values for external devices (ex: resolver). * * Frequency range from 1 kHz to 50 kHz Sine wave amplitude from 0.47 V to 2.26 V
MPC5643L Microcontroller Data Sheet, Rev. 3 18 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Overview
1.3.33
Analog part: *
Analog-to-Digital Converter module (ADC)
The ADC module features are as follows: Two on-chip ADCs -- 12-bit resolution SAR architecture -- Same digital interface as in the MPC5604P family -- A/D Channels: Nine external, Three internal and Four shared with other A/D. Total 16 -- One channel dedicated to each T-sensor to enable temperature reading during application -- Separated reference for each ADC -- Shared analog supply voltage for both ADCs -- One sample and hold unit per ADC -- Adjustable sampling and conversion time Four analog watchdogs comparing ADC results against predefined levels (low, high, range) before results are stored in the appropriate ADC result location Two modes of operation: Motor Control Mode or Regular Mode Regular mode features -- Register based interface with the CPU: one result register per channel -- ADC state machine managing three request flows: regular command, hardware injected command, software injected command -- Selectable priority between software and hardware injected commands -- Four analog watchdogs comparing ADC results against predefined levels (low, high, range) -- DMA compatible interface Motor control mode features -- Triggered mode only -- Four independent result queues (1 x 16 entries, 2 x 8 entries, 1 x 4 entries) -- Result alignment circuitry (left justified; right justified) -- 32-bit read mode allows to have channel ID on one of the 16-bit parts -- DMA compatible interfaces Built-in self-test features triggered by software
Digital part: * * *
*
*
1.3.34
Cross Triggering Unit (CTU)
The ADC cross triggering unit allows automatic generation of ADC conversion requests on user selected conditions without CPU load during the PWM period and with minimized CPU load for dynamic configuration. The CTU implements the following features: * * * * * * * * Cross triggering between ADC, FlexPWM, eTimer, and external pins Double buffered trigger generation unit with as many as eight independent triggers generated from external triggers Maximum operating frequency less than or equal to 120 MHz Trigger generation unit configurable in sequential mode or in triggered mode Trigger delay unit to compensate the delay of external low pass filter Double buffered global trigger unit allowing eTimer synchronization and/or ADC command generation Double buffered ADC command list pointers to minimize ADC-trigger unit update Double buffered ADC conversion command list with as many as 24 ADC commands
MPC5643L Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 19
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Overview
* * *
Each trigger capable of generating consecutive commands ADC conversion command allows control of ADC channel from each ADC, single or synchronous sampling, independent result queue selection DMA support with safety features
1.3.35
Cyclic Redundancy Checker (CRC) Unit
The CRC module is a configurable multiple data flow unit to compute CRC signatures on data written to input register. The CRC unit has the following features: * * Three sets of registers to allow three concurrent contexts with possibly different CRC computations, each with a selectable polynomial and seed Computes 16- or 32-bit wide CRC on the fly (single-cycle computation) and stores result in internal register. The following standard CRC polynomials are implemented: -- x16 + x12 + x5 + 1 [16-bit CRC-CCITT] -- x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1 [32-bit CRC-ethernet(32)] Key engine to be coupled with communication periphery where CRC application is added to allow implementation of safe communication protocol Offloads core from cycle-consuming CRC and helps checking configuration signature for safe start-up or periodic procedures CRC unit connected as peripheral bus on internal peripheral bus DMA support
* * * *
1.3.36
* *
Redundancy Control and Checker Unit (RCCU)
The RCCU checks all outputs of the sphere of replication (addresses, data, control signals). It has the following features: Duplicated module to guarantee highest possible diagnostic coverage (check of checker) Multiple times replicated IPs are used as checkers on the SoR outputs
1.3.37
Junction temperature sensor
The junction temperature sensor is used by the ADC to measure the temperature of the silicon. The key parameters of the junction temperature sensor include: * * Nominal temperature range from -40 to 150 C Software temperature alarm via analog ADC comparator possible
1.3.38
Nexus Port Controller (NPC)
The NPC block provides real-time development support capabilities for this device in compliance with the IEEE-ISTO 5001-2008 standard. This development support is supplied for MCUs without requiring external address and data pins for internal visibility. The NPC block interfaces to the host processor and internal buses to provide development support as per the IEEE-ISTO 5001-2008 Class 3+, including selected features from Class 4 standard. The development support provided includes program trace, data trace, watchpoint trace, ownership trace, run-time access to the MCUs internal memory map and access to the Power Architecture internal registers during halt. The Nexus interface also supports a JTAG only mode using only the JTAG pins. The following features are implemented: * Full and reduced port modes
MPC5643L Microcontroller Data Sheet, Rev. 3 20 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Overview
* * * * * * *
MCKO (message clock out) pin Four or 12 MDO (message data out) pins1 Two MSEO (message start/end out) pins EVTO (event out) pin -- Auxiliary input port EVTI (event in) pin Five-pin JTAG port (JCOMP, TDI, TDO, TMS, and TCK) -- Supports JTAG mode Host processor (e200) development support features -- Data trace via data write messaging (DWM) and data read messaging (DRM). This allows the development tool to trace reads or writes, or both, to selected internal memory resources. -- Ownership trace via ownership trace messaging (OTM). OTM facilitates ownership trace by providing visibility of which process ID or operating system task is activated. An ownership trace message is transmitted when a new process/task is activated, allowing development tools to trace ownership flow. -- Program trace via branch trace messaging (BTM). Branch trace messaging displays program flow discontinuities (direct branches, indirect branches, exceptions, etc.), allowing the development tool to interpolate what transpires between the discontinuities. Thus, static code may be traced. -- Watchpoint messaging (WPM) via the auxiliary port -- Watchpoint trigger enable of program and/or data trace messaging -- Data tracing of instruction fetches via private opcodes
1.3.39
IEEE 1149.1 JTAG Controller (JTAGC)
The JTAGC block provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode. All data input to and output from the JTAGC block is communicated in serial format. The JTAGC block is compliant with the IEEE standard. The JTAG controller provides the following features: * IEEE Test Access Port (TAP) interface with five pins: -- TDI -- TMS -- TCK -- TDO -- JCOMP Selectable modes of operation include JTAGC/debug or normal system operation 5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions: -- BYPASS -- IDCODE -- EXTEST -- SAMPLE -- SAMPLE/PRELOAD Three test data registers: a bypass register, a boundary scan register, and a device identification register. The size of the boundary scan register is parameterized to support a variety of boundary scan chain lengths. TAP controller state machine that controls the operation of the data registers, instruction register and associated circuitry
* *
* *
1. Four MDO pins on 144 LQFP package, 12 MDO pins on 257 MAPBGA package.
MPC5643L Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 21
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Package pinouts and signal descriptions
1.3.40
* *
Voltage regulator / Power Management Unit (PMU)
The on-chip voltage regulator module provides the following features: Single external rail required Single high supply required: nominal 3.3 V both for packaged and Known Good Die option -- Packaged option requires external ballast transistor due to reduced dissipation capacity at high temperature but can use embedded transistor if power dissipation is maintained within package dissipation capacity (lower frequency of operation) -- Known Good Die option uses embedded ballast transistor as dissipation capacity is increased to reduce system cost All I/Os are at same voltage as external supply (3.3 V nominal) Duplicated Low-Voltage Detectors (LVD) to guarantee proper operation at all stages (reset, configuration, normal operation) and, to maximize safety coverage, one LVD can be tested while the other operates (on-line self-testing feature)
* *
1.3.41
* * * *
Built-In Self-Test (BIST) capability
This device includes the following protection against latent faults: Boot-time Memory Built-In Self-Test (MBIST) Boot-time scan-based Logic Built-In Self-Test (LBIST) Run-time ADC Built-In Self-Test (BIST) Run-time Built-In Self Test of LVDs
2
2.1
Package pinouts and signal descriptions
Package pinouts
Figure 2 shows the MPC5643L in the 144 LQFP package. Figure 3 shows the MPC5643L in the 257 MAPBGA package.
MPC5643L Microcontroller Data Sheet, Rev. 3 22 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Freescale Semiconductor
NMI A[6] D[1] F[4] F[5] VDD_HV_IO VSS_HV_IO F[6] MDO0 A[7] C[4] A[8] C[5] A[5] C[7] VDD_HV_REG_0 VSS_LV_COR VDD_LV_COR F[7] F[8] VDD_HV_IO VSS_HV_IO F[9] F[10] F[11] D[9] VDD_HV_OSC VSS_HV_OSC XTAL EXTAL RESET D[8] D[5] D[6] VSS_LV_PLL0_PLL1 VDD_LV_PLL0_PLL1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
144 LQFP package
MPC5643L Microcontroller Data Sheet, Rev. 3
Figure 2. MPC5643L 144 LQFP pinout (top view)
D[7] FCCU_F[0] VDD_LV_COR0_4 VSS_LV_COR0_4 C[1] E[4] B[7] E[5] C[2] E[6] B[8] E[7] E[2] VDD_HV_ADR0 VSS_HV_ADR0 B[9] B[10] B[11] B[12] VDD_HV_ADR1 VSS_HV_ADR1 VDD_HV_ADV0_ADV1 VSS_HV_ADV0_ADV1 B[13] E[9] B[15] E[10] B[14] E[11] C[0] E[12] E[0] BCTRL VDD_LV_COR VSS_LV_COR VDD_HV_PMU 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
A[15] A[14] C[6] FCCU_F[1] D[2] F[3] B[6] VSS_LV_COR A[13] VDD_LV_COR A[9] F[0] VSS_LV_COR VDD_LV_COR VDD_HV_REG_2 D[4] D[3] VSS_HV_IO VDD_HV_IO D[0] C[15] JCOMP A[12] E[15] A[11] E[14] A[10] E[13] B[3] F[14] B[2] F[15] F[13] C[10] B[1] B[0]
Preliminary--Subject to Change Without Notice
A[4] VPP_TEST F[12] D[14] G[3] C[14] G[2] C[13] G[4] D[12] G[6] VDD_HV_FLA VSS_HV_FLA VDD_HV_REG_1 VSS_LV_COR VDD_LV_COR A[3] VDD_HV_IO VSS_HV_IO B[4] TCK TMS B[5] G[5] A[2] G[7] C[12] G[8] C[11] G[9] D[11] G[10] D[10] G[11] A[1] A[0]
Package pinouts and signal descriptions
23
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Package pinouts and signal descriptions Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
1 A
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
VSS VSS VDD_HV F[5]
VSS VSS NC
VDD_HV B[6]
H[2]
H[0]
G[14]
D[3]
C[15]
VDD_HV VSS I[0]
A[12]
H[10]
H[14]
A[10]
B[2]
C[10]
VSS VDD_HV A[4]
VSS VSS F[12]
B
A[14]
F[3]
A[9]
D[4]
D[0]
H[12]
E[15]
E[14]
B[3]
F[13]
B[0]
C
VSS A[15]
FCCU_ F[1] C[6]
D[2]
A[13]
VDD_HV VDD_HV F[0] VDD_HV
JCOMP
H[11]
I[1]
F[14]
B[1]
VSS VPP
_TEST
D
F[4]
VSS
VDD_LV
VSS
NC
A[11]
E[13]
F[15]
VDD_HV NC
D[14]
G[3]
E
MDO0
F[6]
D[1]
NMI
C[14]
G[2]
I[3]
F
H[1]
G[12]
A[7]
A[8]
VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV
NC
C[13]
I[2]
G[4]
G
H[3]
VDD_HV VSS G[15]
C[5]
A[6]
D[12]
H[13]
H[9]
G[6]
H
G[13]
C[4]
A[5]
VSS
VDD_HV VDD_HV VSS H[7]
H[6]
J
F[7]
VDD_HV VDD_HV NC C[7]
VDD_LV VDD_HV NC H[8]
H[15]
K
F[9]
F[8]
A[3]
L
F[10]
F[11]
D[9]
NC
NC
TCK
H[4]
B[4]
M
VDD_HV VDD_HV XTAL VSS RESET FCCU _F[0] VDD_HV VSS 2
D[8]
NC VSS_LV_
PLL
VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV
C[11]
B[5]
TMS
H[5]
N
D[5]
NC
C[12]
A[2]
G[5]
P
VSS EXTAL
D[6]
VDD_LV_
PLL
VDD_LV B[7]
VSS E[6]
B[8] VREFP_
HV_AD0
NC
VSS VREFP_
HV_AD1
VDD_HV B[13]
B[14]
VDD_LV C[0]
VSS BCTRL
VDD_HV A[1]
G[10]
G[8]
G[7]
R
VSS NC
D[7]
B[10]
B[15]
VSS D[10]
D[11]
G[9]
T
VSS VSS 1
C[1]
E[5]
E[7]
VREFN_
HV_AD0
B[11]
VREFN_
HV_AD1
E[9]
E[10]
E[12]
E[0]
A[0]
VDD_HV VSS 16
VSS VSS 17
U
NC 3
E[4] 4
C[2] 5
E[2] 6
B[9] 7
B[12] 8
VDD_HV 9
VSS 10
E[11] 11
NC 12
NC 13
VDD_HV 14
G[11] 15
Figure 3. MPC5643L 257 MAPBGA pinout (top view) Table 3 provides the concatenated pin names (pin muxing) for the pins shown in Figure 2, including the functional group for the pin. Table 3 provides the concatenated ball names (pin muxing) for the pins shown in Figure 3, including the functional group for the pin. For more information, see Table 7.
MPC5643L Microcontroller Data Sheet, Rev. 3 24 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Package pinouts and signal descriptions
2.2
Pin descriptions
The following sections provide signal descriptions and related information about the functionality and configuration for this device.
2.2.1
Concatenated pins
Table 3 provides the concatenated ball names (pin muxing) for the pins shown in Figure 2 and the balls shown in Figure 3, including the functional group for the pin. This table provides a cross-reference for the two packages. Table 3 lists the concatenated ball names (pin muxing) in alphanumeric order for the balls shown in Figure 3, including the functional group. Table 3. Concatenated pin names
Pin Ball No. No. 144 257 LQFP MAPBGA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 E4 G4 E3 D2 D1 VDD_HV1 NMI A[6] / siul_GPIO[6] / dspi1_SCK / siul_EIRQ[6] D[1] / siul_GPIO[49] / etimer1_ETC[2] / ctu0_EXT_TGR / flexray_CA_RX F[4] / siul_GPIO[84] / npc_wrapper_MDO[3] F[5] / siul_GPIO[85] / npc_wrapper_MDO[2] VDD_HV_IO
Concatenated Pin Names
VSS_HV2 VSS_HV_IO E2 E1 F3 H3 F4 G3 H4 K4 J3 VSS_LV
3
F[6] / siul_GPIO[86] / npc_wrapper_MDO[1] MDO0 A[7] / siul_GPIO[7] / dspi1_SOUT / siul_EIRQ[7] C[4] / siul_GPIO[36] / dspi0_CS0 / flexpwm0_X[1] / sscm_DEBUG[4] / siul_EIRQ[22] A[8] / siul_GPIO[8] / dspi1_SIN / siul_EIRQ[8] C[5] / siul_GPIO[37] / dspi0_SCK / sscm_DEBUG[5] / flexpwm0_FAULT[3] / siul_EIRQ[23] A[5] / siul_GPIO[5] / dspi1_CS0 / etimer1_ETC[5] / dspi0_CS7 / siul_EIRQ[5] C[7] / siul_GPIO[39] / flexpwm0_A[1] / sscm_DEBUG[7] / dspi0_SIN VDD_HV_REG_0 VSS_LV_COR VDD_LV_COR F[7] / siul_GPIO[87] / npc_wrapper_MCKO F[8] / siul_GPIO[88] / npc_wrapper_MSEO[1] VDD_HV_IO VSS_HV_IO F[9] / siul_GPIO[89] / npc_wrapper_MSEO[0] F[10] / siul_GPIO[90] / npc_wrapper_EVTO F[11] / siul_GPIO[91] / leo_sor0_EVTI
VDD_LV4 J1 K2 VDD_HV3 VSS_HV K1 L1 L2
4
MPC5643L Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 25
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Package pinouts and signal descriptions
Table 3. Concatenated pin names (continued)
Pin Ball No. No. 144 257 LQFP MAPBGA 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 L3 M1 P1 N1 R1 P2 M3 N3 P3 N4 P4 R4 R2
Concatenated Pin Names
D[9] / siul_GPIO[57] / flexpwm0_X[0] / lin1_TXD VDD_HV_OSC VSS_HV_OSC XTAL5 EXTAL5 RESET D[8] / siul_GPIO[56] / dspi1_CS2 / etimer1_ETC[4] / dspi0_CS5 / flexpwm0_FAULT[3] D[5] / siul_GPIO[53] / dspi0_CS3 / flexpwm0_FAULT[2] D[6] / siul_GPIO[54] / dspi0_CS2 / flexpwm0_X[3] / flexpwm0_FAULT[1] VSS_LV_PLL0_PLL1 VDD_LV_PLL0_PLL1 D[7] / siul_GPIO[55] / dspi1_CS3 / dspi0_CS4 FCCU_F[0]
VDD_LV1 VDD_LV_COR0_4 VSS_LV2 VSS_LV_COR0_4 T4 U4 R5 T5 U5 R6 P7 T6 U6 R7 T7 U7 R8 T8 U8 R9 T9 U9 C[1] / siul_GPIO[33] E[4] / siul_GPIO[68] B[7] / siul_GPIO[23] / lin0_RXD E[5] / siul_GPIO[69] C[2] / siul_GPIO[34] E[6] / siul_GPIO[70] B[8] / siul_GPIO[24] / etimer0_ETC[5] E[7] / siul_GPIO[71] E[2] / siul_GPIO[66] VDD_HV_ADR0 VSS_HV_ADR0 B[9] / siul_GPIO[25] B[10] / siul_GPIO[26] B[11] / siul_GPIO[27] B[12] / siul_GPIO[28] VDD_HV_ADR1 VSS_HV_ADR1 VDD_HV_ADV
MPC5643L Microcontroller Data Sheet, Rev. 3 26 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Package pinouts and signal descriptions
Table 3. Concatenated pin names (continued)
Pin Ball No. No. 144 257 LQFP MAPBGA 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 U10 R10 T10 R11 T11 P11 U11 R12 T12 T13 R13 VDD_LV VSS_LV U14 T14 R14 U15 T15 P15 R16 R17 M14 P16 N15 P17 N16 N17 M15 M16 L15 L17
1
Concatenated Pin Names
VSS_HV_ADV B[13] / siul_GPIO[29] / lin1_RXD E[9] / siul_GPIO[73] B[15] / siul_GPIO[31] / siul_EIRQ[20] E[10] / siul_GPIO[74] B[14] / siul_GPIO[30] / etimer0_ETC[4] / siul_EIRQ[19] E[11] / siul_GPIO[75] C[0] / siul_GPIO[32] E[12] / siul_GPIO[76] E[0] / siul_GPIO[64] BCTRL VDD_LV_COR VSS_LV_COR VDD_HV_PMU A[0] / siul_GPIO[0] / etimer0_ETC[0] / dspi2_SCK / siul_EIRQ[0] A[1] / siul_GPIO[1] / etimer0_ETC[1] / dspi2_SOUT / siul_EIRQ[1] G[11] / siul_GPIO[107] / flexray_DBG3 / flexpwm0_FAULT[3] D[10] / siul_GPIO[58] / flexpwm0_A[0] / etimer0_ETC[0] G[10] / siul_GPIO[106] / flexray_DBG2 / dspi2_CS3 / flexpwm0_FAULT[2] D[11] / siul_GPIO[59] / flexpwm0_B[0] / etimer0_ETC[1] G[9] / siul_GPIO[105] / flexray_DBG1 / dspi1_CS1 / flexpwm0_FAULT[1] / siul_EIRQ[29] C[11] / siul_GPIO[43] / etimer0_ETC[4] / dspi2_CS2 G[8] / siul_GPIO[104] / flexray_DBG0 / dspi0_CS1 / flexpwm0_FAULT[0] / siul_EIRQ[21] C[12] / siul_GPIO[44] / etimer0_ETC[5] / dspi2_CS3 G[7] / siul_GPIO[103] / flexpwm0_B[3] A[2] / siul_GPIO[2] / etimer0_ETC[2] / flexpwm0_A[3] / dspi2_SIN / mc_rgm_ABS[0] / siul_EIRQ[2] G[5] / siul_GPIO[101] / flexpwm0_X[3] / dspi2_CS3 B[5] / siul_GPIO[21] / jtagc_TDI TMS TCK B[4] / siul_GPIO[20] / jtagc_TDO
2
VSS_HV4 VSS_HV_IO
MPC5643L Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 27
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Package pinouts and signal descriptions
Table 3. Concatenated pin names (continued)
Pin Ball No. No. 144 257 LQFP MAPBGA 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 VDD_HV3 VDD_HV_IO K17 A[3] / siul_GPIO[3] / etimer0_ETC[3] / dspi2_CS0 / flexpwm0_B[3] / mc_rgm_ABS[2] / siul_EIRQ[3]
Concatenated Pin Names
VDD_LV1 VDD_LV_COR VSS_LV2 VSS_LV_COR H15 J16 H16 G17 G14 F17 F15 E16 E15 D17 D16 C17 D15 C16 B15 C14 A15 B14 D13 A14 C13 B13 D12 A13 B12 D11 B11 VDD_HV_REG_1 VSS_HV_FLA VDD_HV_FLA G[6] / siul_GPIO[102] / flexpwm0_A[3] D[12] / siul_GPIO[60] / flexpwm0_X[1] / lin1_RXD G[4] / siul_GPIO[100] / flexpwm0_B[2] / etimer0_ETC[5] C[13] / siul_GPIO[45] / etimer1_ETC[1] / ctu0_EXT_IN / flexpwm0_EXT_SYNC G[2] / siul_GPIO[98] / flexpwm0_X[2] / dspi1_CS1 C[14] / siul_GPIO[46] / etimer1_ETC[2] / ctu0_EXT_TGR G[3] / siul_GPIO[99] / flexpwm0_A[2] / etimer0_ETC[4] D[14] / siul_GPIO[62] / flexpwm0_B[1] / etimer0_ETC[3] F[12] / siul_GPIO[92] / etimer1_ETC[3] / siul_EIRQ[30] VPP_TEST6 A[4] / siul_GPIO[4] / etimer1_ETC[0] / dspi2_CS1 / etimer0_ETC[4] / mc_rgm_FAB / siul_EIRQ[4] B[0] / siul_GPIO[16] / can0_TXD / etimer1_ETC[2] / sscm_DEBUG[0] / siul_EIRQ[15] B[1] / siul_GPIO[17] / etimer1_ETC[3] / sscm_DEBUG[1] / can0_RXD / can1_RXD / siul_EIRQ[16] C[10] / siul_GPIO[42] / dspi2_CS2 / flexpwm0_A[3] / flexpwm0_FAULT[1] F[13] / siul_GPIO[93] / etimer1_ETC[4] / siul_EIRQ[31] F[15] / siul_GPIO[95] / lin1_RXD B[2] / siul_GPIO[18] / lin0_TXD / sscm_DEBUG[2] / siul_EIRQ[17] F[14] / siul_GPIO[94] / lin1_TXD B[3] / siul_GPIO[19] / sscm_DEBUG[3] / lin0_RXD E[13] / siul_GPIO[77] / etimer0_ETC[5] / dspi2_CS3 / siul_EIRQ[25] A[10] / siul_GPIO[10] / dspi2_CS0 / flexpwm0_B[0] / flexpwm0_X[2] / siul_EIRQ[9] E[14] / siul_GPIO[78] / etimer1_ETC[5] / siul_EIRQ[26] A[11] / siul_GPIO[11] / dspi2_SCK / flexpwm0_A[0] / flexpwm0_A[2] / siul_EIRQ[10] E[15] / siul_GPIO[79] / dspi0_CS1 / siul_EIRQ[27]
MPC5643L Microcontroller Data Sheet, Rev. 3 28 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Package pinouts and signal descriptions
Table 3. Concatenated pin names (continued)
Pin Ball No. No. 144 257 LQFP MAPBGA 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 A10 C10 A8 B8 VDD_HV3 VSS_HV A7 B7 C7 VDD_LV1
4
Concatenated Pin Names
A[12] / siul_GPIO[12] / dspi2_SOUT / flexpwm0_A[2] / flexpwm0_B[2] / siul_EIRQ[11] JCOMP C[15] / siul_GPIO[47] / flexray_CA_TR_EN / etimer1_ETC[0] / flexpwm0_A[1] / ctu0_EXT_IN / flexpwm0_EXT_SYNC D[0] / siul_GPIO[48] / flexray_CA_TX / etimer1_ETC[1] / flexpwm0_B[1] VDD_HV_IO VSS_HV_IO D[3] / siul_GPIO[51] / flexray_CB_TX / etimer1_ETC[4] / flexpwm0_A[3] D[4] / siul_GPIO[52] / flexray_CB_TR_EN / etimer1_ETC[5] / flexpwm0_B[3] VDD_HV_REG_2 VDD_LV_COR
VSS_LV2 VSS_LV_COR D7 B6 VDD_LV C6
1
F[0] / siul_GPIO[80] / flexpwm0_A[1] / etimer0_ETC[2] / siul_EIRQ[28] A[9] / siul_GPIO[9] / dspi2_CS1 / flexpwm0_B[3] / flexpwm0_FAULT[0] VDD_LV_COR A[13] / siul_GPIO[13] / flexpwm0_B[2] / dspi2_SIN / flexpwm0_FAULT[0] / siul_EIRQ[12]
VSS_LV2 VSS_LV_COR B3 B5 C5 C4 D4 B4 D3 B[6] / siul_GPIO[22] / mc_cgl_clk_out / dspi2_CS2 / siul_EIRQ[18] F[3] / siul_GPIO[83] / dspi0_CS6 D[2] / siul_GPIO[50] / etimer1_ETC[3] / flexpwm0_X[3] / flexray_CB_RX FCCU_F[1] C[6] / siul_GPIO[38] / dspi0_SOUT / flexpwm0_B[1] / sscm_DEBUG[6] / siul_EIRQ[24] A[14] / siul_GPIO[14] / can1_TXD / etimer1_ETC[4] / siul_EIRQ[13] A[15] / siul_GPIO[15] / etimer1_ETC[5] / can1_RXD / can0_RXD / siul_EIRQ[14]
NOTES: 1 VDD_HV balls are tied together on the 257 MAPBGA substrate. 2 VSS_HV balls are tied together on the 257 MAPBGA substrate. 3 VSS_LV balls are tied together on the 257 MAPBGA substrate. 4 VDD_LV balls are tied together on the 257 MAPBGA substrate. 5 The XTAL and EXTAL pins have different functions from the pins with these names on the MPC5604P. 6 VPP_TEST should always be tied to ground (VSS) for normal operations.
MPC5643L Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 29
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Package pinouts and signal descriptions
Table 4. 257 MAPBGA concatenated ball names
Ball No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 VSS_HV_IO_RING VSS_HV_IO_RING VDD_HV_IO_RING H[2] / siul_GPIO[114] / npc_wrapper_MDO[5] H[0] / siul_GPIO[112] / npc_wrapper_MDO[7] G[14] / siul_GPIO[110] / npc_wrapper_MDO[9] D[3] / siul_GPIO[51] / flexray_CB_TX / etimer1_ETC[4] / flexpwm0_A[3] C[15] / siul_GPIO[47] / flexray_CA_TR_EN / etimer1_ETC[0] / flexpwm0_A[1] / ctu0_EXT_IN / flexpwm0_EXT_SYNC VDD_HV_IO_RING A[12] / siul_GPIO[12] / dspi2_MOSI / flexpwm0_A[2] / flexpwm0_B[2] / siul_EIRQ[11] H[10] / siul_GPIO[122] / flexpwm1_X[2] / etimer2_ETC[2] H[14] / siul_GPIO[126] / flexpwm1_A[3] / etimer2_ETC[4] A[10] / siul_GPIO[10] / dspi2_CS0 / flexpwm0_B[0] / flexpwm0_X[2] / siul_EIRQ[9] B[2] / siul_GPIO[18] / lin0_TXD / sscm_DEBUG[2] / siul_EIRQ[17] C[10] / siul_GPIO[42] / dspi2_CS2 / flexpwm0_A[3] / flexpwm0_FAULT[1] VSS_HV_IO_RING VSS_HV_IO_RING VSS_HV_IO_RING VSS_HV_IO_RING B[6] / siul_GPIO[22] / mc_cgl_clk_out / dspi2_CS2 / siul_EIRQ[18] A[14] / siul_GPIO[14] / can1_TXD / etimer1_ETC[4] / siul_EIRQ[13] F[3] / siul_GPIO[83] / dspi0_CS6 A[9] / siul_GPIO[9] / dspi2_CS1 / flexpwm0_B[3] / flexpwm0_FAULT[0] D[4] / siul_GPIO[52] / flexray_CB_TR_EN / etimer1_ETC[5] / flexpwm0_B[3] D[0] / siul_GPIO[48] / flexray_CA_TX / etimer1_ETC[1] / flexpwm0_B[1] VSS_HV_IO_RING H[12] / siul_GPIO[124] / flexpwm1_B[2] E[15] / siul_GPIO[79] / dspi0_CS1 / siul_EIRQ[27] E[14] / siul_GPIO[78] / etimer1_ETC[5] / siul_EIRQ[26] B[3] / siul_GPIO[19] / sscm_DEBUG[3] / lin0_RXD F[13] / siul_GPIO[93] / etimer1_ETC[4] / siul_EIRQ[31] B[0] / siul_GPIO[16] / can0_TXD / etimer1_ETC[2] / sscm_DEBUG[0] / siul_EIRQ[15] VDD_HV_IO_RING VSS_HV_IO_RING Concatenated Pin Names
MPC5643L Microcontroller Data Sheet, Rev. 3 30 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Package pinouts and signal descriptions
Table 4. 257 MAPBGA concatenated ball names (continued)
Ball No. C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 E1 VDD_HV_IO_RING NC1 VSS_HV_IO_RING FCCU_F[1] D[2] / siul_GPIO[50] / etimer1_ETC[3] / flexpwm0_X[3] / flexray_CB_RX A[13] / siul_GPIO[13] / flexpwm0_B[2] / dspi2_MISO / flexpwm0_FAULT[0] / siul_EIRQ[12] VDD_HV_REG_2 VDD_HV_REG_2 I[0] / siul_GPIO[128] / etimer2_ETC[0] / dspi0_CS4 / flexpwm1_FAULT[0] JCOMP H[11] / siul_GPIO[123] / flexpwm1_A[2] I[1] / siul_GPIO[129] / etimer2_ETC[1] / dspi0_CS5 / flexpwm1_FAULT[1] F[14] / siul_GPIO[94] / lin1_TXD B[1] / siul_GPIO[17] / etimer1_ETC[3] / sscm_DEBUG[1] / can0_RXD / can1_RXD / siul_EIRQ[16] VSS_HV_IO_RING A[4] / siul_GPIO[4] / etimer1_ETC[0] / dspi2_CS1 / etimer0_ETC[4] / mc_rgm_FAB / siul_EIRQ[4] F[12] / siul_GPIO[92] / etimer1_ETC[3] / siul_EIRQ[30] F[5] / siul_GPIO[85] / npc_wrapper_MDO[2] F[4] / siul_GPIO[84] / npc_wrapper_MDO[3] A[15] / siul_GPIO[15] / etimer1_ETC[5] / can1_RXD / can0_RXD / siul_EIRQ[14] C[6] / siul_GPIO[38] / dspi0_MOSI / flexpwm0_B[1] / sscm_DEBUG[6] / siul_EIRQ[24] VSS_LV_CORE_RING VDD_LV_CORE_RING F[0] / siul_GPIO[80] / flexpwm0_A[1] / etimer0_ETC[2] / siul_EIRQ[28] VDD_HV_IO_RING VSS_HV_IO_RING NC1 A[11] / siul_GPIO[11] / dspi2_SCK / flexpwm0_A[0] / flexpwm0_A[2] / siul_EIRQ[10] E[13] / siul_GPIO[77] / etimer0_ETC[5] / dspi2_CS3 / siul_EIRQ[25] F[15] / siul_GPIO[95] / lin1_RXD VDD_HV_IO_RING VPP_TEST2 D[14] / siul_GPIO[62] / flexpwm0_B[1] / etimer0_ETC[3] G[3] / siul_GPIO[99] / flexpwm0_A[2] / etimer0_ETC[4] MDO0 Concatenated Pin Names
MPC5643L Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 31
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Package pinouts and signal descriptions
Table 4. 257 MAPBGA concatenated ball names (continued)
Ball No. E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 G1 G2 Concatenated Pin Names F[6] / siul_GPIO[86] / npc_wrapper_MDO[1] D[1] / siul_GPIO[49] / etimer1_ETC[2] / ctu0_EXT_TGR / flexray_CA_RX NMI NP3 NP3 NP3 NP3 NP3 NP3 NP3 NP3 NP3 NC1 C[14] / siul_GPIO[46] / etimer1_ETC[2] / ctu0_EXT_TGR G[2] / siul_GPIO[98] / flexpwm0_X[2] / dspi1_CS1 I[3] / siul_GPIO[131] / etimer2_ETC[3] / dspi0_CS7 / ctu0_EXT_TGR / flexpwm1_FAULT[3] H[1] / siul_GPIO[113] / npc_wrapper_MDO[6] G[12] / siul_GPIO[108] / npc_wrapper_MDO[11] A[7] / siul_GPIO[7] / dspi1_MOSI / siul_EIRQ[7] A[8] / siul_GPIO[8] / dspi1_MISO / siul_EIRQ[8] NP3 VDD_LV_CORE_RING VDD_LV_CORE_RING VDD_LV_CORE_RING VDD_LV_CORE_RING VDD_LV_CORE_RING VDD_LV_CORE_RING VDD_LV_CORE_RING NP3 NC1 C[13] / siul_GPIO[45] / etimer1_ETC[1] / ctu0_EXT_IN / flexpwm0_EXT_SYNC I[2] / siul_GPIO[130] / etimer2_ETC[2] / dspi0_CS6 / flexpwm1_FAULT[2] G[4] / siul_GPIO[100] / flexpwm0_B[2] / etimer0_ETC[5] H[3] / siul_GPIO[115] / npc_wrapper_MDO[4] VDD_HV_IO_RING
MPC5643L Microcontroller Data Sheet, Rev. 3 32 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Package pinouts and signal descriptions
Table 4. 257 MAPBGA concatenated ball names (continued)
Ball No. G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 J1 J2 J3 Concatenated Pin Names C[5] / siul_GPIO[37] / dspi0_SCK / sscm_DEBUG[5] / flexpwm0_FAULT[3] / siul_EIRQ[23] A[6] / siul_GPIO[6] / dspi1_SCK / siul_EIRQ[6] NP3 VDD_LV_CORE_RING VSS_LV_CORE_RING VSS_LV_CORE_RING VSS_LV_CORE_RING VSS_LV_CORE_RING VSS_LV_CORE_RING VDD_LV_CORE_RING NP3 D[12] / siul_GPIO[60] / flexpwm0_X[1] / lin1_RXD H[13] / siul_GPIO[125] / flexpwm1_X[3] / etimer2_ETC[3] H[9] / siul_GPIO[121] / flexpwm1_B[1] / dspi0_CS7 G[6] / siul_GPIO[102] / flexpwm0_A[3] G[13] / siul_GPIO[109] / npc_wrapper_MDO[10] VSS_HV_IO_RING C[4] / siul_GPIO[36] / dspi0_CS0 / flexpwm0_X[1] / sscm_DEBUG[4] / siul_EIRQ[22] A[5] / siul_GPIO[5] / dspi1_CS0 / etimer1_ETC[5] / dspi0_CS7 / siul_EIRQ[5] NP3 VDD_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VDD_LV NP3 VSS_LV VDD_HV_REG_1 VDD_HV_FLA0 H[6] / siul_GPIO[118] / flexpwm1_B[0] / dspi0_CS5 F[7] / siul_GPIO[87] / npc_wrapper_MCKO G[15] / siul_GPIO[111] / npc_wrapper_MDO[8] VDD_HV_REG_0
MPC5643L Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 33
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Package pinouts and signal descriptions
Table 4. 257 MAPBGA concatenated ball names (continued)
Ball No. J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 L1 L2 L3 L4 VDD_HV_REG_0 NP3 VDD_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VDD_LV NP3 VDD_LV VDD_HV_REG_1 VSS_HV_FLA0 H[15] / siul_GPIO[127] / flexpwm1_B[3] / etimer2_ETC[5] F[9] / siul_GPIO[89] / npc_wrapper_MSEO_B[0] F[8] / siul_GPIO[88] / npc_wrapper_MSEO_B[1] NC1 C[7] / siul_GPIO[39] / flexpwm0_A[1] / sscm_DEBUG[7] / dspi0_MISO NP3 VDD_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VDD_LV NP3 NC1 H[8] / siul_GPIO[120] / flexpwm1_A[1] / dspi0_CS6 H[7] / siul_GPIO[119] / flexpwm1_X[1] / etimer2_ETC[1] A[3] / siul_GPIO[3] / etimer0_ETC[3] / dspi2_CS0 / flexpwm0_B[3] / mc_rgm_ABS[2] / siul_EIRQ[3] F[10] / siul_GPIO[90] / npc_wrapper_EVTO_B F[11] / siul_GPIO[91] / leo_sor_proxy_EVTI_B D[9] / siul_GPIO[57] / flexpwm0_X[0] / lin1_TXD NC1 Concatenated Pin Names
MPC5643L Microcontroller Data Sheet, Rev. 3 34 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Package pinouts and signal descriptions
Table 4. 257 MAPBGA concatenated ball names (continued)
Ball No. L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 N1 N2 N3 N4 N5 NP3 VDD_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VDD_LV NP3 NC1 TCK H[4] / siul_GPIO[116] / flexpwm1_X[0] / etimer2_ETC[0] B[4] / siul_GPIO[20] / jtagc_TDO VDD_HV_OSC0 VDD_HV_IO_RING D[8] / siul_GPIO[56] / dspi1_CS2 / etimer1_ETC[4] / dspi0_CS5 / flexpwm0_FAULT[3] NC1 NP3 VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV NP3 C[11] / siul_GPIO[43] / etimer0_ETC[4] / dspi2_CS2 B[5] / siul_GPIO[21] / jtagc_TDI TMS H[5] / siul_GPIO[117] / flexpwm1_A[0] / dspi0_CS4 XTAL VSS_HV_IO_RING D[5] / siul_GPIO[53] / dspi0_CS3 / flexpwm0_FAULT[2] VSS_LV_PLL0_PLL1 NP3 Concatenated Pin Names
MPC5643L Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 35
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Package pinouts and signal descriptions
Table 4. 257 MAPBGA concatenated ball names (continued)
Ball No. N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 R1 R2 R3 R4 R5 R6 NP3 NP3 NP3 NP3 NP3 NP3 NP3 NP3 NC1 C[12] / siul_GPIO[44] / etimer0_ETC[5] / dspi2_CS3 A[2] / siul_GPIO[2] / etimer0_ETC[2] / flexpwm0_A[3] / dspi2_MISO / mc_rgm_ABS[0] / siul_EIRQ[2] G[5] / siul_GPIO[101] / flexpwm0_X[3] / dspi2_CS3 VSS_HV_OSC0 RESET D[6] / siul_GPIO[54] / dspi0_CS2 / flexpwm0_X[3] / flexpwm0_FAULT[1] VDD_LV_PLL0_PLL1 VDD_LV_CORE_RING VSS_LV_CORE_RING B[8] / siul_GPIO[24] / etimer0_ETC[5] NC1 VSS_HV_IO_RING VDD_HV_IO_RING B[14] / siul_GPIO[30] / etimer0_ETC[4] / siul_EIRQ[19] VDD_LV_CORE_RING VSS_LV_CORE_RING VDD_HV_IO_RING G[10] / siul_GPIO[106] / flexray_DBG2 / dspi2_CS3 / flexpwm0_FAULT[2] G[8] / siul_GPIO[104] / flexray_DBG0 / dspi0_CS1 / flexpwm0_FAULT[0] / siul_EIRQ[21] G[7] / siul_GPIO[103] / flexpwm0_B[3] EXTAL FCCU_F[0] VSS_HV_IO_RING D[7] / siul_GPIO[55] / dspi1_CS3 / dspi0_CS4 B[7] / siul_GPIO[23] / lin0_RXD E[6] / siul_GPIO[70] Concatenated Pin Names
MPC5643L Microcontroller Data Sheet, Rev. 3 36 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Package pinouts and signal descriptions
Table 4. 257 MAPBGA concatenated ball names (continued)
Ball No. R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 U1 U2 U3 U4 U5 U6 U7 VDD_HV_ADR0 B[10] / siul_GPIO[26] VDD_HV_ADR1 B[13] / siul_GPIO[29] / lin1_RXD B[15] / siul_GPIO[31] / siul_EIRQ[20] C[0] / siul_GPIO[32] BCTRL A[1] / siul_GPIO[1] / etimer0_ETC[1] / dspi2_MOSI / siul_EIRQ[1] VSS_HV_IO_RING D[11] / siul_GPIO[59] / flexpwm0_B[0] / etimer0_ETC[1] G[9] / siul_GPIO[105] / flexray_DBG1 / dspi1_CS1 / flexpwm0_FAULT[1] / siul_EIRQ[29] VSS_HV_IO_RING VDD_HV_IO_RING NC1 C[1] / siul_GPIO[33] E[5] / siul_GPIO[69] E[7] / siul_GPIO[71] VSS_HV_ADR0 B[11] / siul_GPIO[27] VSS_HV_ADR1 E[9] / siul_GPIO[73] E[10] / siul_GPIO[74] E[12] / siul_GPIO[76] E[0] / siul_GPIO[64] A[0] / siul_GPIO[0] / etimer0_ETC[0] / dspi2_SCK / siul_EIRQ[0] D[10] / siul_GPIO[58] / flexpwm0_A[0] / etimer0_ETC[0] VDD_HV_IO_RING VSS_HV_IO_RING VSS_HV_IO_RING VSS_HV_IO_RING NC1 E[4] / siul_GPIO[68] C[2] / siul_GPIO[34] E[2] / siul_GPIO[66] B[9] / siul_GPIO[25] Concatenated Pin Names
MPC5643L Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Package pinouts and signal descriptions
Table 4. 257 MAPBGA concatenated ball names (continued)
Ball No. U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 B[12] / siul_GPIO[28] VDD_HV_ADV VSS_HV_ADV E[11] / siul_GPIO[75] NC1 NC1 VDD_HV_PMU G[11] / siul_GPIO[107] / flexray_DBG3 / flexpwm0_FAULT[3] VSS_HV_IO_RING VSS_HV_IO_RING Concatenated Pin Names
NOTES: 1 Not connected. 2V PP_TEST should always be tied to ground (VSS) for normal operations. 3 Ball not populated on substrate.
2.2.2
Power supply and reference voltage pins
Table 5. Supply pins
Supply Package 257 144 MAPBGA LQFP
Table 5 lists the power supply and reference voltage for this device.
Symbol
Description VREG control and power supply pins
BCTRL VDD_LV_COR VSS_LV_COR VDD_HV_PMU
Voltage regulator external NPN Ballast base control pin Voltage regulator supply voltage Core regulator ground Core regulator supply ADC0/ADC1 reference voltage and ADC supply
69 70 71 72
R13 VDD_LV1 VSS_LV2 U14
VDD_HV_ADR0 VSS_HV_ADR0 VDD_HV_ADR1 VSS_HV_ADR1 VDD_HV_ADV VSS_HV_ADV
ADC0 high reference voltage ADC0 low reference voltage ADC1 high reference voltage ADC1 low reference voltage ADC voltage supply for ADC0 and ADC1 ADC ground for ADC0 and ADC1 Power Supply pins (3.3 V)
50 51 56 57 58 59
R7 T7 R9 T9 U9 U10
VDD_HV_IO
3.3 V Input/Output supply voltage
6
VDD_HV3
MPC5643L Microcontroller Data Sheet, Rev. 3 38 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Package pinouts and signal descriptions
Table 5. Supply pins (continued)
Supply Package 257 144 MAPBGA LQFP 7 16 21 22 27 28 72 90 91 95 96 97 107 126 127 130 Power Supply pins (1.2 V) VSS_LV_COR VSS_LV_COR Decoupling pins for core logic. Decoupling capacitor must be connected between these pins and the nearest VDD_LV_COR pin. VDD_LV_COR Decoupling pins for core logic. Decoupling capacitor must be connected between these pins and the nearest VSS_LV_COR pin. VSS_LV_PLL0_PLL1 / 1.2 V Decoupling pins for on-chip PLL modules. Decoupling capacitor must be connected between this pin and VDD_LV_PLL. VDD_LV_PLL0_PLL1 Decoupling pins for on-chip PLL modules. Decoupling capacitor must be connected between this pin and VSS_LV_PLL. VDD_LV_COR Decoupling pins for core logic. Decoupling capacitor must be connected between these pins and the nearest VSS_LV_COR pin. VSS_LV_COR Decoupling pins for core logic. Decoupling capacitor must be connected between these pins and the nearest VDD_LV_COR pin. 17 VSS_HV2 VSS_HV4 J3 VDD_HV3 VSS_HV4 M1 P1 U14 VSS_HV4 VDD_HV3 H15 J16 H16 D15 VDD_HV3 VSS_HV4 C7
Symbol VSS_HV_IO 3.3 V Input/Output ground
Description
VDD_HV_REG_0 VDD_HV_REG_0 VDD_HV_IO VSS_HV_IO VDD_HV_OSC VSS_HV_OSC VDD_HV_PMU VSS_HV_IO VDD_HV_IO 3.3 V Input/Output supply voltage 3.3 V Input/Output ground Crystal oscillator amplifier supply voltage Crystal oscillator amplifier ground VDD_HV_PMU 3.3 V Input/Output ground 3.3 V Input/Output supply voltage
VDD_HV_REG_1 VDD_HV_REG_1 VSS_HV_FLA VDD_HV_FLA VPP_TEST5 VDD_HV_IO VSS_HV_IO VSS_HV_FLA VDD_HV_FLA VPP_TEST VDD_HV_IO VSS_HV_IO
VDD_HV_REG_2 VDD_HV_REG_2
VDD_LV_COR
18
VDD_LV1
VSS 1V2
35
N4
VDD 1V2
36
P4
VDD_LV_COR
39
VDD_LV1
VSS_LV_COR
40
VSS_LV2
MPC5643L Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 39
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Package pinouts and signal descriptions
Table 5. Supply pins (continued)
Supply Package 257 144 MAPBGA LQFP
Symbol
Description VDD_LV_COR Decoupling pins for core logic and Regulator feedback. Decoupling capacitor must be connected between this pins and VSS_LV_REGCOR. VSS_LV_REGCOR0 Decoupling pins for core logic and Regulator feedback. Decoupling capacitor must be connected between this pins and VDD_LV_REGCOR. VDD_LV_COR Decoupling pins for core logic. Decoupling capacitor must be connected between these pins and the nearest VSS_LV_COR pin. VSS_LV_COR / 1.2 V Decoupling pins for core logic. Decoupling capacitor must be connected between these pins and the nearest VDD_LV_COR pin. VDD_LV_COR Decoupling pins for core logic. Decoupling capacitor must be connected between these pins and the nearest VDD_LV_COR pin. VSS_LV_COR Decoupling pins for core logic. Decoupling capacitor must be connected between these pins and the nearest VDD_LV_COR pin. VDD_LV_COR / Decoupling pins for core logic. Decoupling capacitor must be connected between these pins and the nearest VDD_LV_COR pin. VSS_LV_COR / Decoupling pins for core logic. Decoupling capacitor must be connected between these pins and the nearest VDD_LV_COR pin.
VDD_LV_COR
70
VDD_LV1
VSS_LV_COR
71
VSS_LV2
VDD_LV_COR
93
VDD_LV1
VSS_LV_COR
94
VSS_LV2
VDD 1V2
131
VDD_LV1
VSS 1V2
132
VSS_LV2
VDD 1V2
135
VDD_LV1
VSS 1V2
137
VSS_LV2
NOTES: 1 VDD_LV balls are tied together on the 257 MAPBGA substrate. 2 VSS_LV balls are tied together on the 257 MAPBGA substrate. 3 VDD_HV balls are tied together on the 257 MAPBGA substrate. 4 VSS_HV balls are tied together on the 257 MAPBGA substrate. 5 VPP_TEST must always be tied to ground (VSS) for normal operations.
MPC5643L Microcontroller Data Sheet, Rev. 3 40 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Package pinouts and signal descriptions
2.2.3
System pins
Table 6 and Table 7 contain information on pin functions for this device. The pins listed in Table 6 are single-function pins. The pins shown in Table 7 are multi-function pins, programmable via their respective Pad Configuration Register (PCR) values. Table 6. System pins
Package Symbol Description Direction 144pin 257ball
Dedicated pins MDO0 NMI XTALIN XTALOUT TMS TCK JCOMP Nexus Message Data Output -- line 0 Non Maskable Interrupt Input for oscillator amplifier circuit and internal clock generator Oscillator amplifier output JTAG state machine control JTAG clock JTAG compliance select Reset pin RESET Bidirectional reset with Schmitt-Trigger characteristics and noise filter. This Bidirectional pin has medium drive strength. 31 P2 Output only Input only Input only Output only Input only Input only Input only 9 1 29 30 87 88 123 E1 E4 N1 R1 M16 L15 C10
2.2.4
Pin muxing
Table 7 defines the pin list and muxing for this device. Each row of Table 7 shows all the possible configurations for each pin, via the alternate functions. The alternate functions are shown in the Alternate Function column and are labeled ALT0, ALT1, ALT2, and ALT3. The default function assigned to each pin after reset is indicated by ALT0. Some pins have more than four alternate functions. These additional alternate functions are shown in the Other Functions column. This column also contains information related to the External Interrupt capability and the boot configuration. Pins marked as external interrupt capable can also be used to resume from STOP and HALT mode.
NOTE
Pins labeled "NC" are to be left unconnected. Any connection to an external circuit or voltage may cause unpredictable device behavior or damage. Pins labeled "Reserved" are to be tied to ground. Not doing so may cause unpredictable device behavior.
MPC5643L Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 41
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Package pinouts and signal descriptions
42 Port Pin PCR Register IBE = Alternate Function2,3 Peripheral5 04 Function PCR[0] Preliminary--Subject to Change Without Notice Freescale Semiconductor A[0] ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 SIU Lite eTimer0 DSPI2 -- SIU Lite eTimer0 DSPI2 -- SIU Lite eTimer0 -- FlexPWM0 SIU Lite eTimer0 DSPI2 FlexPWM0 SIU Lite eTimer1 DSPI2 eTimer0 SIU Lite DSPI1 eTimer1 DSPI0 SIU Lite DSPI1 -- -- SIU Lite DSPI1 -- -- GPIO[0] ETC[0] SCK -- GPIO[1] ETC[1] MOSI -- GPIO[2] ETC[2] -- A[3] GPIO[3] ETC[3] CS0 B[3] GPIO[4] ETC[0] CS1 ETC[4] GPIO[5] CS0 ETC[5] CS7 GPIO[6] SCK -- -- GPIO[7] SOUT -- -- PCR[1] A[1] MPC5643L Data Sheet, Rev. 3 PCR[2] A[2] PCR[3] A[3] PCR[4] A[4] PCR[5] A[5] PCR[6] A[6] PCR[7] A[7]
Table 7. Pin muxing
Functions IBE = 1 (always inputs) I/O Direction Peripheral Functions Pad Speed1 Pin
SRC SRC 144- 257=0 =1 pin ball
Port A (16-bit) I/O I/O O -- I/O I/O O -- I/O I/O -- I/O I/O I/O I/O I/O I/O I/O O I/O I/O I/O I/O O I/O I/O -- -- I/O O -- -- SIU Lite Ext. IRQ #0 (input) S M 73 T14
SIU Lite Ext. IRQ #1 (input) S M 74
R14
SIU Lite
Ext. IRQ #2 (input) DSPI2 SIN (input) Boot pin ABS[0] (input) Weak pull down during reset Ext. IRQ #3 (input) Boot pin ABS[2] (input) Weak pull down during reset Ext. IRQ #4 (input) Boot pin FAB (input) Weak pull down during reset
N16 S M 84
SIU Lite
K17 S M 92
SIU Lite
C16 S M 108
SIU Lite Ext. IRQ #5 (input) S M 14
H4
SIU Lite Ext. IRQ #6 (input) S M 2
G4
SIU Lite Ext. IRQ #7 (input) S M 10
F3
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Table 7. Pin muxing (continued)
Functions Port Pin PCR Register IBE = Alternate Function2,3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 Peripheral5 SIU Lite -- -- -- SIU Lite DSPI2 -- FlexPWM0 SIU Lite DSPI2 FlexPWM0 FlexPWM0 SIU Lite DSPI2 FlexPWM0 FlexPWM0 SIU Lite DSPI2 FlexPWM0 FlexPWM0 SIU Lite -- FlexPWM0 -- SIU Lite CAN1 eTimer1 -- SIU Lite -- eTimer1 -- 04 I/O Direction I/O -- -- -- I/O O -- I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/O I/O I/O -- I/O -- I/O O I/O -- I/O -- I/O -- SIU Lite Ext. IRQ #9 (input) S M 118 Peripheral SIU Lite Ext. IRQ #8 (input) DSPI1 SIN (input) S M 12 IBE = 1 (always inputs) Functions Pad Speed1 Pin
Freescale Semiconductor Preliminary--Subject to Change Without Notice 43 MPC5643L Data Sheet, Rev. 3
Function GPIO[8] -- -- -- GPIO[9] CS1 -- B[3] GPIO[10] CS0 B[0] X[2] GPIO[11] SCK A[0] A[2] GPIO[12] SOUT A[2] B[2] GPIO[13] -- B[2] -- GPIO[14] TXD ETC[4] -- GPIO[15] -- ETC[5] --
SRC SRC 144- 257=0 =1 pin ball F4
PCR[8] A[8]
PCR[9] A[9]
B6 FlexPWM0 FAULT[0] (input) S M 134
PCR[10] A[10]
A13
PCR[11] A[11]
SIU Lite Ext. IRQ #10 (input) S M 120
D11
PCR[12] A[12]
SIU Lite Ext. IRQ #11 (input) S M 122
A10
Package pinouts and signal descriptions
PCR[13] A[13]
SIU Lite
Ext. IRQ #12 (input) DSPI2 SIN (input) FlexPWM0 FAULT[0] (input)
C6 S M 136
PCR[14] A[14]
SIU Lite Ext. IRQ #13 (input) S M 143
B4
PCR[15] A[15]
SIU Lite
Ext. IRQ #14 (input) CAN1 RXD (input) CAN0 RXD (input)
D3 S M 144
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Table 7. Pin muxing (continued)
Functions Port Pin PCR Register IBE = Alternate Function2,3 Peripheral5 04 I/O Direction Peripheral IBE = 1 (always inputs) Functions Pad Speed1 Pin
Package pinouts and signal descriptions
44 PCR[16] Preliminary--Subject to Change Without Notice Freescale Semiconductor B[0] ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 SIU Lite CAN0 eTimer1 SSCM SIU Lite -- eTimer1 SSCM SIU Lite LIN0 -- SSCM SIU Lite -- -- SSCM SIU Lite JTAG -- -- SIU Lite -- -- -- SIU Lite MC_CGM DSPI2 -- SIU Lite -- -- -- PCR[17] B[1] MPC5643L Data Sheet, Rev. 3 PCR[18] B[2] PCR[19] B[3] PCR[20] B[4]
6
Function
SRC SRC 144- 257=0 =1 pin ball
Port B (16-bit) GPIO[16] TXD ETC[2] DEBUG[0] GPIO[17] -- ETC[3] DEBUG[1] GPIO[18] TXD -- DEBUG[2] GPIO[19] -- -- DEBUG[3] GPIO[20] TDO -- -- GPIO[21] -- -- -- GPIO[22] CLKOUT CS2 -- GPIO[23] -- -- -- I/O O I/O I/O I/O -- I/O I/O I/O O -- I/O I/O -- -- I/O I/O O -- -- I/O -- -- -- I/O O O -- I -- -- -- SIU Lite Ext. IRQ #18 (input) S M 138 SIU Lite Ext. IRQ #15 (input) S M 109 B15
SIU Lite
Ext. IRQ #16 (input) CAN0 RXD (input) CAN1 RXD (input)
C14 S M 110
SIU Lite Ext. IRQ #17 (input) S M 114
A14
B13 LIN0 RXD (input) S M 116
L17 -- S F 89
PCR[21] B[5]
M15 JTAG0 TDI (input) S M 86
PCR[22] B[6]
B3
PCR[23] B[7]
R5 LIN0 RXD (input) ADC0 AN[0] --
7
--
6
43
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Table 7. Pin muxing (continued)
Functions Port Pin PCR Register IBE = Alternate Function2,3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 Peripheral5 SIU Lite -- -- -- SIU Lite -- -- -- SIU Lite -- -- -- SIU Lite -- -- -- SIU Lite -- -- -- SIU Lite -- -- -- SIU Lite -- -- -- SIU Lite -- -- -- 04 I/O Direction I -- -- -- I -- -- -- I -- -- -- I -- -- -- I -- -- -- I -- -- -- I -- -- -- I -- -- -- Peripheral IBE = 1 (always inputs) Functions Pad Speed1 Pin
Freescale Semiconductor Preliminary--Subject to Change Without Notice 45 MPC5643L Data Sheet, Rev. 3
Function GPIO[24] -- -- -- GPIO[25] -- -- -- GPIO[26] -- -- -- GPIO[27] -- -- -- GPIO[28] -- -- -- GPIO[29] -- -- -- GPIO[30] -- -- -- GPIO[31] -- -- --
SRC SRC 144- 257=0 =1 pin ball P7
PCR[24] B[8]
eTimer0 ETC[5] ADC0 AN[1] (input)
--6
--6
47
PCR[25] B[9]
U7 ADC0 - ADC1 AN[11] (input) --6 --6 52
PCR[26] B[10]
R8 ADC0 - ADC1 AN[12] (input) --6 --6 53
PCR[27] B[11]
T8 ADC0 - ADC1 AN[13] (input) --6 --6 54
PCR[28] B[12]
U8 ADC0 - ADC1 AN[14] (input) --6 --6 55 Package pinouts and signal descriptions
PCR[29] B[13]
R10 ADC1 AN[0] (input) LIN1 RXD (input) --6 --6 60
PCR[30] B[14]
Ext. IRQ #19 (input) ADC1 AN[1] (input) eTimer0 ETC[4]
P11 --
6
--6
64
PCR[31] B[15]
R11 Ext. IRQ #20 (input) ADC1 AN[2] --
6
--6
62
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Table 7. Pin muxing (continued)
Functions Port Pin PCR Register IBE = Alternate Function2,3 Peripheral5 04 I/O Direction Peripheral IBE = 1 (always inputs) Functions Pad Speed1 Pin
Package pinouts and signal descriptions
46 PCR[32] Preliminary--Subject to Change Without Notice Freescale Semiconductor C[0] ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 SIU Lite -- -- -- SIU Lite -- -- -- SIU Lite -- -- -- SIU Lite DSPI0 FlexPWM0 SSCM SIU Lite DSPI0 -- SSCM SIU Lite DSPI0 FlexPWM0 SSCM SIU Lite -- FlexPWM0 SSCM SIU Lite DSPI2 -- FlexPWM0 PCR[33] C[1] MPC5643L Data Sheet, Rev. 3 PCR[34] C[2] PCR[36] C[4] PCR[37] C[5] PCR[38] C[6] PCR[39] C[7] PCR[42] C[10]
Function
SRC SRC 144- 257=0 =1 pin ball
Port C (16-bit) GPIO[32] -- -- -- GPIO[33] -- -- -- GPIO[34] -- -- -- GPIO[36] CS0 X[1] DEBUG[4] GPIO[37] SCK -- DEBUG[5] GPIO[38] SOUT B[1] DEBUG[6] GPIO[39] -- A[1] DEBUG[7] GPIO[42] CS2 -- A[3] I -- -- -- I -- -- -- I -- -- -- I/O I/O I/O I/O I/O I/O -- I/O I/O O I/O I/O I/O -- I/O I/O I/O O -- I/O SIU Lite Ext. IRQ #22 (input) S M 11 R12 ADC1 AN[3] (input) --
6
--6
66
T4 ADC0 AN[2] (input) --
6
--6
41
U5 ADC0 AN[3] (input) --
6
--6
45
H3
SIU Lite Ext. IRQ #23 (input) FlexPWM0 FAULT[3] (input) SIU Lite Ext. IRQ #24 (input) S M 142 S M 13
G3
D4
K4 DSPI0 SIN (input) S M 15
A15 FlexPWM0 FAULT[1] (input) S M 111
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Table 7. Pin muxing (continued)
Functions Port Pin PCR Register IBE = Alternate Function2,3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 Peripheral5 SIU Lite eTimer0 DSPI2 -- SIU Lite eTimer0 DSPI2 -- SIU Lite eTimer1 -- -- SIU Lite eTimer1 CTU0 -- SIU Lite FlexRay0 eTimer1 FlexPWM0 04 I/O Direction I/O I/O O -- I/O I/O O -- I/O I/O -- -- I/O I/O O -- I/O O I/O I/O Port D (16-bit) PCR[48] D[0] ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 SIU Lite FlexRay0 eTimer1 FlexPWM0 SIU Lite -- eTimer1 CTU0 SIU Lite -- eTimer1 FlexPWM0 GPIO[48] CA_TX ETC[1] B[1] GPIO[49] -- ETC[2] EXT_TRG GPIO[50] -- ETC[3] X[3] I/O O I/O I/O I/O -- I/O O I/O -- I/O I/O B8 -- S SYM 125 Peripheral IBE = 1 (always inputs) Functions Pad Speed1 Pin
Freescale Semiconductor Preliminary--Subject to Change Without Notice 47 MPC5643L Data Sheet, Rev. 3
Function GPIO[43] ETC[4] CS2 -- GPIO[44] ETC[5] CS3 -- GPIO[45] ETC[1] -- -- GPIO[46] ETC[2] EXT TGR -- GPIO[47] CA_TR_ EN ETC[0] A[1]
SRC SRC 144- 257=0 =1 pin ball M14
PCR[43] C[11]
--
S
M
80
PCR[44] C[12]
N15 -- S M 82
PCR[45] C[13]
F15 FlexPWM0 ext. sync (input) CTU0 EXT_IN (input) S M 101
PCR[46] C[14]
E15 -- S M 103
PCR[47] C[15]
FlexPWM0 ext. sync (input) CTU0 EXT_IN (input)
A8 S SYM 124 Package pinouts and signal descriptions
PCR[49] D[1]
E3 FlexRay0 CA_RX (input) S M 3
PCR[50] D[2]
C5 FlexRay0 CB_RX (input) S M 140
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Table 7. Pin muxing (continued)
Functions Port Pin PCR Register IBE = Alternate Function2,3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 Peripheral5 SIU Lite FlexRay0 eTimer1 FlexPWM0 SIU Lite FlexRay0 eTimer1 FlexPWM0 SIU Lite DSPI0 -- -- SIU Lite DSPI0 -- FlexPWM0 SIU Lite DSPI1 -- DSPI0 SIU Lite DSPI1 eTimer1 DSPI0 SIU Lite FlexPWM0 LIN1 -- SIU Lite FlexPWM0 -- -- 04 I/O Direction I/O O I/O I/O I/O O I/O I/O I/O O -- -- I/O O -- I/O I/O O -- O I/O O I/O O I/O I/O O -- I/O I/O -- -- Peripheral IBE = 1 (always inputs) Functions Pad Speed1 Pin
Package pinouts and signal descriptions
48 PCR[51] D[3] Preliminary--Subject to Change Without Notice Freescale Semiconductor PCR[52] D[4] MPC5643L Data Sheet, Rev. 3 PCR[53] D[5] PCR[54] D[6] PCR[55] D[7] PCR[56] D[8] PCR[57] D[9] PCR[58] D[10]
Function GPIO[51] CB_TX ETC[4] A[3] GPIO[52] CB_TR_EN ETC[5] B[3] GPIO[53] CS3 -- -- GPIO[54] CS2 -- X[3] GPIO[55] CS3 -- CS4 GPIO[56] CS2 ETC[4] CS5 GPIO[57] X[0] TXD -- GPIO[58] A[0] -- --
SRC SRC 144- 257=0 =1 pin ball A7
--
S
SYM
128
B7 -- S SYM 129
N3 FlexPWM0 FAULT[2] (input) S M 33
P3 FlexPWM0 FAULT[1] (input) S M 34
R4 SWG ANAOUT S M 37
M3 FlexPWM0 FAULT[3] (input) S M 32
L3 -- S M 26
T15 eTimer0 ETC[0] S M 76
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Table 7. Pin muxing (continued)
Functions Port Pin PCR Register IBE = Alternate Function2,3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 Peripheral5 SIU Lite FlexPWM0 -- -- SIU Lite FlexPWM0 -- -- SIU Lite FlexPWM0 -- -- 04 I/O Direction I/O I/O -- -- I/O I/O -- -- I/O I/O -- -- Port E (16-bit) PCR[64] E[0] ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 SIU Lite -- -- -- SIU Lite -- -- -- SIU Lite -- -- -- SIU Lite -- -- -- SIU Lite -- -- -- GPIO[64] -- -- -- GPIO[66] -- -- -- GPIO[68] -- -- -- GPIO[69] -- -- -- GPIO[70] -- -- -- I -- -- -- I -- -- -- I -- -- -- I -- -- -- I -- -- -- T13 ADC1 AN[5] (input) --
6
Freescale Semiconductor Preliminary--Subject to Change Without Notice 49 MPC5643L Data Sheet, Rev. 3
IBE = 1 (always inputs) Peripheral Functions
Pad Speed1
Pin
Function GPIO[59] B[0] -- -- GPIO[60] X[1] -- -- GPIO[62] B[1] -- --
SRC SRC 144- 257=0 =1 pin ball R16
PCR[59] D[11]
eTimer0 ETC[1]
S
M
78
PCR[60] D[12]
G14 LIN1 RXD (input) S M 99
PCR[62] D[14]
D16 eTimer0 ETC[3] S M 105
--6
68
PCR[66] E[2]
U6 ADC0 AN[5] (input) --
6
--6
49
Package pinouts and signal descriptions
PCR[68] E[4]
U4 ADC0 AN[7] (input) --
6
--6
42
PCR[69] E[5]
T5 ADC0 AN[8] (input) --
6
--6
44
PCR[70] E[6]
R6 ADC0 AN[4] (input) --
6
--
6
46
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Table 7. Pin muxing (continued)
Functions Port Pin PCR Register IBE = Alternate Function2,3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 Peripheral5 SIU Lite -- -- -- SIU Lite -- -- -- SIU Lite -- -- -- SIU Lite -- -- -- SIU Lite -- -- -- SIU Lite eTimer0 DSPI3 -- SIU Lite eTimer1 -- -- SIU Lite DSPI0 -- -- 04 I/O Direction I -- -- -- I -- -- -- I -- -- -- I -- -- -- I -- -- -- I/O I/O O -- I/O I/O -- -- I/O O -- -- Peripheral IBE = 1 (always inputs) Functions Pad Speed1 Pin
Package pinouts and signal descriptions
50 PCR[71] E[7] Preliminary--Subject to Change Without Notice Freescale Semiconductor PCR[73] E[9] MPC5643L Data Sheet, Rev. 3 PCR[74] E[10] PCR[75] E[11] PCR[76] E[12] PCR[77] E[13] PCR[78] E[14] PCR[79] E[15]
Function GPIO[71] -- -- -- GPIO[73] -- -- -- GPIO[74] -- -- -- GPIO[75] -- -- -- GPIO[76] -- -- -- GPIO[77] ETC[5] CS3 -- GPIO[78] ETC[5] -- -- GPIO[79] CS1 -- --
SRC SRC 144- 257=0 =1 pin ball T6
ADC0 AN[6] (input)
--
6
--6
48
T10 ADC1 AN[7] (input) --
6
--6
61
T11 -- ADC1 AN[8] (input) --
6
--6
63
U11 -- ADC1 AN[4] (input) --
6
--6
65
T12 -- ADC1 AN[6] (input) --
6
--6
67
D12 -- Ext. IRQ #25 (input) S M 117
B12 -- Ext. IRQ #26 (input) S M 119
B11 -- Ext. IRQ #27 (input) S M 121
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Table 7. Pin muxing (continued)
Functions Port Pin PCR Register IBE = Alternate Function2,3 Peripheral5 04 I/O Direction Peripheral IBE = 1 (always inputs) Functions Pad Speed1 Pin
Freescale Semiconductor Preliminary--Subject to Change Without Notice 51 MPC5643L Data Sheet, Rev. 3
Function
SRC SRC 144- 257=0 =1 pin ball
Port F (16-bit) PCR[80] F[0] ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 SIU Lite FlexPWM0 -- -- SIU Lite DSPI0 -- -- SIU Lite -- Nexus0 -- SIU Lite -- Nexus0 -- SIU Lite -- Nexus0 -- SIU Lite -- Nexus0 -- SIU Lite -- Nexus0 -- SIU Lite -- Nexus0 -- GPIO[80] A[1] -- -- GPIO[83] CS6 -- -- GPIO[84] -- MDO[3] -- GPIO[85] -- MDO[2] -- GPIO[86] -- MDO[1] -- GPIO[87] -- MCKO -- GPIO[88] -- MSEO1 -- GPIO[89] -- MSEO0 -- I/O I/O -- -- I/O O -- -- I/O -- O -- I/O -- O -- I/O -- O -- I/O -- O -- I/O -- O -- I/O -- O -- SIU Lite Ext. IRQ #28 (input) eTimer0 ETC[2] S M 133 D7
PCR[83] F[3]
B5 -- S M 139
PCR[84] F[4]
D2 -- -- S F 4
PCR[85] F[5]
D1 -- -- S F 5
PCR[86] F[6]
E2 -- -- S F 8 Package pinouts and signal descriptions
PCR[87] F[7]
J1 -- -- S F 19
PCR[88] F[8]
K2 -- -- S F 20
PCR[89] F[9]
K1 -- -- S F 23
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Table 7. Pin muxing (continued)
Functions Port Pin PCR Register IBE = Alternate Function2,3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 Peripheral5 SIU Lite -- Nexus0 -- SIU Lite -- Nexus0 -- SIU Lite eTimer1 -- -- SIU Lite eTimer1 -- -- SIU Lite LIN1 -- -- SIU Lite -- -- -- 04 I/O Direction I/O -- O -- I/O -- I -- I/O I/O -- -- I/O I/O -- -- I/O O -- -- I/O -- -- -- Port G (16-bit) SIU Lite Ext. IRQ #30 (input) S M 106 Peripheral IBE = 1 (always inputs) Functions Pad Speed1 Pin
Package pinouts and signal descriptions
52 PCR[90] F[10] Preliminary--Subject to Change Without Notice Freescale Semiconductor PCR[91] F[11] MPC5643L Data Sheet, Rev. 3 PCR[92] F[12] PCR[93] F[13] PCR[94] F[14] PCR[95] F[15] PCR[96] G[0] ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 SIU Lite FCCU0 -- -- SIU Lite FCCU0 -- -- PCR[97] G[1]
Function GPIO[90] -- EVTO -- GPIO[91] -- NEX_EN -- GPIO[92] ETC[3] -- -- GPIO[93] ETC[4] -- -- GPIO[94] TXD -- -- GPIO[95] -- -- --
SRC SRC 144- 257=0 =1 pin ball L1
--
--
S
F
24
L2 Nexus0 EVTI (input) S M 25
C17
SIU Lite Ext. IRQ #31 (input) S M 112
B14
C13 -- -- S M 115
D13 LIN1 RXD (input) S M 113
GPIO[96] F[0] -- -- GPIO[97] F[1] -- --
I/O I/O -- -- I/O I/O -- --
R2 Ext. IRQ #30 (input) S M 38
C4 Ext. IRQ #31 (input) S M 141
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Table 7. Pin muxing (continued)
Functions Port Pin PCR Register IBE = Alternate Function2,3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 Peripheral5 SIU Lite FlexPWM0 DSPI1 -- SIU Lite FlexPWM0 -- -- SIU Lite FlexPWM0 -- -- SIU Lite FlexPWM0 DSPI2 -- SIU Lite FlexPWM0 -- -- SIU Lite FlexPWM0 -- -- SIU Lite FlexRay DSPI0 -- SIU Lite FlexRay DSPI1 -- 04 I/O Direction I/O I/O O -- I/O I/O -- -- I/O I/O -- -- I/O I/O O -- I/O I/O -- -- I/O I/O -- -- I/O O O -- I/O O O -- Peripheral IBE = 1 (always inputs) Functions Pad Speed1 Pin
Freescale Semiconductor Preliminary--Subject to Change Without Notice 53 MPC5643L Data Sheet, Rev. 3
Function GPIO[98] X[2] CS1 -- GPIO[99] A[2] -- -- GPIO[100] B[2] -- -- GPIO[101] X[3] CS2 -- GPIO[102] A[3] -- -- GPIO[103] B[3] -- -- GPIO[104] DBG0 CS1 -- GPIO[105] DBG1 CS1 --
SRC SRC 144- 257=0 =1 pin ball E16
PCR[98] G[2]
--
--
S
M
102
PCR[99] G[3]
D17 -- eTimer ETC[4] S M 104
PCR[100] G[4]
F17 eTimer ETC[5] S M 100
PCR[101] G[5]
N17 -- -- S M 85
PCR[102] G[6]
G17 -- -- S M 98 Package pinouts and signal descriptions
PCR[103] G[7]
P17 -- -- S M 83
PCR[104] G[8]
P16 Ext. IRQ #21 (input) FlexPWM0 FAULT[0] (input) S M 81
PCR[105] G[9]
R17 Ext. IRQ #29 (input) FlexPWM0 FAULT[1] (input) S M 79
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Table 7. Pin muxing (continued)
Functions Port Pin PCR Register IBE = Alternate Function2,3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 Peripheral5 SIU Lite FlexRay DSPI2 -- SIU Lite FlexRay -- -- SIU Lite -- Nexus0 -- SIU Lite -- Nexus0 -- SIU Lite -- Nexus0 -- SIU Lite -- Nexus0 -- 04 I/O Direction I/O O O -- I/O O -- -- I/O -- O -- I/O -- O -- I/O -- O -- I/O -- O -- Port H (16-bit) Peripheral IBE = 1 (always inputs) Functions Pad Speed1 Pin
Package pinouts and signal descriptions
54 PCR[106] G[10] Preliminary--Subject to Change Without Notice Freescale Semiconductor PCR[107] G[11] MPC5643L Data Sheet, Rev. 3 PCR[108] G[12] PCR[109] G[13] PCR[110] G[14] PCR[111] G[15] PCR[112] H[0] ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 SIU Lite -- Nexus0 -- SIU Lite -- Nexus0 -- PCR[113] H[1]
Function GPIO[106] DBG2 CS3 -- GPIO[107] DBG3 -- -- GPIO[108] -- MDO[11] -- GPIO[109] -- MDO[10] -- GPIO[110] -- MDO[9] -- GPIO[111] -- MDO[8] --
SRC SRC 144- 257=0 =1 pin ball P15
FlexPWM0 FAULT[2] (input)
S
M
77
U15 FlexPWM0 FAULT[3] (input) S M 75
F2 -- -- --
H1 -- -- --
A6 -- -- --
J2 -- -- --
GPIO[112] -- MDO[7] -- GPIO[113] -- MDO[6] --
I/O -- O -- I/O -- O --
A5 -- -- --
F1 -- -- --
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Table 7. Pin muxing (continued)
Functions Port Pin PCR Register IBE = Alternate Function2,3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 Peripheral5 SIU Lite -- Nexus0 -- SIU Lite -- Nexus0 -- SIU Lite FlexPWM1 eTimer2 -- SIU Lite FlexPWM1 -- DSPI0 SIU Lite FlexPWM1 -- DSPI0 SIU Lite FlexPWM1 eTimer2 -- SIU Lite FlexPWM1 -- DSPI0 SIU Lite FlexPWM1 -- DSPI0 04 I/O Direction I/O -- O -- I/O -- O -- I/O I/O I/O -- I/O I/O -- O I/O I/O -- O I/O I/O I/O -- I/O I/O -- O I/O I/O -- O Peripheral IBE = 1 (always inputs) Functions Pad Speed1 Pin
Freescale Semiconductor Preliminary--Subject to Change Without Notice 55 MPC5643L Data Sheet, Rev. 3
Function GPIO[114] -- MDO[5] -- GPIO[115] -- MDO[4] -- GPIO[116] X[0] ETC[0] -- GPIO[117] A[0] -- CS4 GPIO[118] B[0] -- CS5 GPIO[119] X[1] ETC[1] -- GPIO[120] A[1] -- CS6 GPIO[121] B[1] -- CS7
SRC SRC 144- 257=0 =1 pin ball A4
PCR[114] H[2]
--
--
--
PCR[115] H[3]
G1 -- -- --
PCR[116] H[4]
L16 -- -- --
PCR[117] H[5]
M17 -- -- --
PCR[118] H[6]
H17 -- -- -- Package pinouts and signal descriptions
PCR[119] H[7]
K16 -- -- --
PCR[120] H[8]
K15 -- -- --
PCR[121] H[9]
G16 -- -- --
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Table 7. Pin muxing (continued)
Functions Port Pin PCR Register IBE = Alternate Function2,3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 Peripheral5 SIU Lite FlexPWM1 eTimer2 -- SIU Lite FlexPWM1 04 I/O Direction I/O I/O I/O -- I/O I/O Peripheral IBE = 1 (always inputs) Functions Pad Speed1 Pin
Package pinouts and signal descriptions
56 PCR[122] H[10] Preliminary--Subject to Change Without Notice Freescale Semiconductor PCR[123] H[11] MPC5643L Data Sheet, Rev. 3 PCR[124] H[12] SIU Lite FlexPWM1 PCR[125] H[13] SIU Lite FlexPWM1 eTimer2 -- SIU Lite FlexPWM1 eTimer2 -- SIU Lite FlexPWM1 eTimer2 -- PCR[126] H[14] PCR[127] H[15] PCR[128] I[0] ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 SIU Lite eTimer2 DSPI0 -- SIU Lite eTimer2 DSPI0 -- PCR[129] I[1]
Function GPIO[122] X[2] ETC[2] -- GPIO[123] A[2]
SRC SRC 144- 257=0 =1 pin ball A11
--
--
--
C11 -- -- --
GPIO[124] B[2]
I/O I/O -- -- I/O I/O I/O -- I/O I/O I/O -- I/O I/O I/O -- Port I (4-bit)
B10 -- -- --
GPIO[125] X[3] ETC[3] -- GPIO[126] A[3] ETC[4] -- GPIO[127] B[3] ETC[5] --
G15 -- -- --
A12 -- -- --
J17 -- -- --
GPIO[128] ETC[0] CS4 -- GPIO[129] ETC[1] CS5 --
I/O I/O O -- I/O I/O O --
FlexPWM1 Fault[0] --
C9
FlexPWM1 Fault[1] --
C12
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Table 7. Pin muxing (continued)
Functions Port Pin PCR Register IBE = Alternate Function2,3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 Peripheral5 SIU Lite eTimer2 DSPI0 -- SIU Lite eTimer2 DSPI0 CTU0 04 I/O Direction I/O I/O O -- I/O I/O O O Peripheral FlexPWM1 Fault[2 -- IBE = 1 (always inputs) Functions Pad Speed1 Pin
Freescale Semiconductor Preliminary--Subject to Change Without Notice 57 MPC5643L Data Sheet, Rev. 3
Function GPIO[130] ETC[2] CS6 -- GPIO[131] ETC[3] CS7 EXT. TGR
SRC SRC 144- 257=0 =1 pin ball F16
PCR[130] I[2]
PCR[131] I[3]
FlexPWM1 Fault[3] -- E17
NOTES: 1 Programmable via the SRC (Slew Rate Control) bit in the respective Pad Configuration Register. S = Slow, M = Medium, F = Fast, SYM = Symmetric (FlexRay). 2 ALT0 is the primary (default) function for each port after reset. 3 Alternate functions are chosen by setting the values of the PCR[PA] bitfields inside the SIU module. - PCR[PA] = 00 ALT0 - PCR[PA] = 01 ALT1 - PCR[PA] = 10 ALT2 - PCR[PA] = 11 ALT3 This bitfield selects the output and input/output functions. To use one of the input-only functions, the PCR[IBE] bit must be written to `1', regardless of the value of PCR[PA]. For this reason, the value corresponding to an input-only function is reported as "--". 4 Alternate input functions are chosen by setting the values of the PCR[IBE] bit in the SIU module. - PCR[IBE] = 0 Input/out alternate functions (default) - PCR[IBE] = 1 Input-only alternate functions To use one of the input-only functions, the PCR[IBE] bit must be written to `1', regardless of the value of PCR[PA]. For this reason, the value corresponding to an input-only function is reported as "--". 5 Module included on the device. 6 The default function of this pin out of reset is ALT1 (TDO). 7 Input-only. Pad speed does not apply.
Package pinouts and signal descriptions
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Electrical characteristics
3
3.1
Electrical characteristics
Introduction
This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for this device. This device is designed to operate at 120 MHz. The electrical specifications are preliminary and are from previous designs, design simulations, or initial evaluation. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be published after complete characterization and device qualifications have been completed. The "Symbol" column of the electrical parameter and timings tables contains an additional column containing "SR", "P", "C", "T", or "D". * * "SR" identifies system requirements--conditions that must be provided to ensure normal device operation. An example is the input voltage of a voltage regulator. "P", "C", "T", or "D" apply only to controller characteristics--specifications that define normal device operation. They specify how each characteristic is guaranteed. -- P: parameter is guaranteed by production testing of each individual device. -- C: parameter is guaranteed by design characterization. Measurements are taken from a statistically relevant sample size across process variations. -- T: parameter is guaranteed by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values are shown in the typical ("typ") column are within this category. -- D: parameters are derived mainly from simulations.
3.2
Absolute maximum ratings
Table 8. Absolute maximum ratings1
Symbol VDD_HV_REG VSS_HV_REG VDD_HV_IOx VSS_HV_IOx VDD_HV_FLA VSS_HV_FLA VDD_HV_OSC VSS_HV_OSC SR SR SR SR SR SR SR SR Parameter 3.3 V voltage regulator supply voltage 3.3 V voltage regulator reference voltage 3.3 V input/output supply voltage Input/output ground voltage 3.3 V flash supply voltage Flash ground 3.3 V crystal oscillator amplifier supply voltage 3.3 V crystal oscillator amplifier reference voltage 3.3 V / 5.0 V ADC0 high reference voltage 3.3 V / 5.0 V ADC1 high reference voltage ADC0 ground and low reference voltage ADC1 ground and low reference voltage 3.3 V ADC supply voltage 3.3 V ADC supply ground Conditions -- -- -- -- -- -- -- -- -- -- -- -- Min -0.3 -0.1 -0.3 -0.1 -0.3 -0.1 -0.3 -0.1 -0.3 -0.1 -0.3 -0.1 Max2 4.03, 4 0.1 3.63, 4 0.1 3.63, 4 0.1 4.03, 4 0.1 6.0 0.1 4.03, 4 0.1 Unit V V V V V V V V V V V V
VDD_HV_ADR05 SR VDD_HV_ADR1 VSS_HV_ADR0 VSS_HV_ADR1 VDD_HV_ADV VSS_HV_ADV SR SR SR
MPC5643L Microcontroller Data Sheet, Rev. 3 58 Preliminary--Subject to Change Without Notice Freescale Semiconductor
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Electrical characteristics
Table 8. Absolute maximum ratings1 (continued)
Symbol TVDD VIN IINJPAD IINJSUM TSTG SR SR SR SR SR Parameter Slope characteristics on all VDD during power up Voltage on any pin with respect to ground (VSS_HV_IOx) Injected input current on any pin during overload condition Absolute sum of all injected input currents during overload condition Storage temperature Conditions -- -- Relative to VDD -- -- -- Min 0.5 -0.3 -0.3 -10 -50 -55 Max2 Unit
3.0 x 106 V/s (3.0 V/sec) 6.0 VDD + 0.36 10 50 150 V
mA mA C
NOTES: 1 Functional operating conditions are given in the DC electrical characteristics. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or cause permanent damage to the device. 2 Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device stress have not yet been determined. 3 5.3 V for 10 hours cumulative over lifetime of device, 3.3 V +10% for time remaining. 4 Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance. 5V DD_HV_ADR0 and VDD_HV_ADR1 cannot be operated be operated at different voltages, and need to be supplied by the same voltage source. 6 Only when V DD < 5.2 V.
3.3
Recommended operating conditions
Table 9. Recommended operating conditions (3.3 V)
Symbol VDD_HV_REG VSS_HV_REG VDD_HV_IOx VSS_HV_IOx VDD_HV_FLA VSS_HV_FLA VDD_HV_OSC VSS_HV_OSC VDD_HV_ADR02 VDD_HV_ADR1 VDD_HV_ADV VSS_HV_AD0 VSS_HV_AD1 VSS_HV_ADV VDD_LV_REGCOR3 Parameter SR 3.3 V voltage regulator supply voltage SR 3.3 V voltage regulator reference voltage SR 3.3 V input/output supply voltage SR Input/output ground voltage SR 3.3 V flash supply voltage SR Flash ground SR 3.3 V crystal oscillator amplifier supply voltage SR 3.3 V crystal oscillator amplifier reference voltage SR 3.3 V / 5.0 V ADC0 high reference voltage 3.3 V / 5.0 V ADC1 high reference voltage SR 3.3 V ADC supply voltage SR ADC0 ground and low reference voltage ADC1 ground and low reference voltage SR 3.3 V ADC supply ground SR Internal supply voltage Conditions -- -- -- -- -- -- -- -- -- -- -- -- -- Min 3.0 0 3.0 0 3.0 0 3.0 0 Max1 3.6 0 3.6 0 3.6 0 3.6 0 Unit V V V V V V V V V V V V V
4.5 to 5.5 or 3.0 to 3.3 3.0 0 0 -- 3.6 0 0 --
MPC5643L Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 59
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Electrical characteristics
Table 9. Recommended operating conditions (3.3 V) (continued)
Symbol Parameter Conditions -- -- -- -- -- fCPU 120 MHz -- Min 0 -- 0 -- 0 -40 -40 Max1 0 -- 0 -- 0 125 150 Unit V V V V V C C
VSS_LV_REGCOR4 SR Internal reference voltage VDD_LV_CORx2 VSS_LV_CORx3 VDD_LV_PLL2 VSS_LV_PLL TA TJ
3
SR Internal supply voltage SR Internal reference voltage SR Internal supply voltage SR Internal reference voltage SR Ambient temperature under bias SR Junction temperature under bias
NOTES: 1 Full functionality cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed. 2V DD_HV_ADR0 and VDD_HV_ADR1 cannot be operated be operated at different voltages, and need to be supplied by the same voltage source. 3 Can be connected to emitter of external NPN. Low voltage supplies are not under user control. They are produced by an on-chip voltage regulator. 4 For the device to function properly, the low voltage grounds (V SS_LV_xxx) must be shorted to high voltage grounds (VSS_HV_xxx) and the low voltage supply pins (VDD_LV_xxx) must be connected to the external ballast emitter, if one is used.
3.4
No. 1 2 5 6 7
Thermal characteristics
Table 10. Thermal characteristics for 144 LQFP package1
Symbol RJA RJA RJB RJC JT D D D D D Parameter Thermal resistance junction-to-ambient natural convection2 Thermal resistance junction-to-ambient natural convection2 Thermal resistance junction-to-board3 Thermal resistance junction-to-case4 Junction-to-package-top natural convection
5
Conditions Single layer board - 1s Four layer board - 2s2p -- -- --
Value Unit TBD C/W TBD C/W TBD C/W TBD C/W TBD C/W
NOTES: 1 Thermal characteristics are targets based on simulation that are subject to change per device characterization. 2 Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. 3 Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. 4 Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. 5 Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
MPC5643L Microcontroller Data Sheet, Rev. 3 60 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Electrical characteristics
Table 11. Thermal characteristics for 257 MAPBGA package1
No. 1 2 5 6 7 Symbol RJA RJA RJB RJC JT D D D D D Parameter Thermal resistance junction-to-ambient natural convection2 Thermal resistance junction-to-ambient natural convection2 Thermal resistance junction-to-board3 Thermal resistance junction-to-case4 Junction-to-package-top natural convection
5
Conditions Single layer board - 1s Four layer board - 2s2p -- -- --
Value Unit TBD C/W TBD C/W TBD C/W TBD C/W TBD C/W
NOTES: 1 Thermal characteristics are targets based on simulation that are subject to change per device characterization. 2 Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. 3 Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. 4 Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. 5 Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
3.4.1
General notes for specifications at maximum junction temperature
TJ = TA + (RJA x PD) Eqn. 1
An estimation of the chip junction temperature, TJ, can be obtained from Equation 1:
where: = ambient temperature for the package (oC) TA RJA = junction to ambient thermal resistance (oC/W) PD = power dissipation in the package (W)
The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. When a heat sink is used, the thermal resistance is expressed in Equation 2 as the sum of a junction to case thermal resistance and a case to ambient thermal resistance:
RJA = RJC + RCA where: RJA = junction to ambient thermal resistance (C/W) RJC = junction to case thermal resistance (C/W) RCA = case to ambient thermal resistance (C/W)
MPC5643L Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice
Eqn. 2
61
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Electrical characteristics
RJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RCA. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal Characterization Parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using Equation 3: TJ = TT + (JT x PD) Eqn. 3
where: = thermocouple temperature on top of the package (C) TT JT = thermal characterization parameter (C/W) PD = power dissipation in the package (W)
The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.
3.4.1.1
References
Semiconductor Equipment and Materials International 3081 Zanker Road San Jose, CA 95134 USA (408) 943-6900 MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or 303-397-7956. JEDEC specifications are available on the WEB at http://www.jedec.org.
1. C.E. Triplett and B. Joiner, "An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module," Proceedings of SemiTherm, San Diego, 1998, pp. 47-54. 2. G. Kromann, S. Shidore, and S. Addison, "Thermal Modeling of a PBGA for Air-Cooled Applications," Electronic Packaging and Production, pp. 53-58, March 1998. 3. B. Joiner and V. Adams, "Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling," Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.
MPC5643L Microcontroller Data Sheet, Rev. 3 62 Preliminary--Subject to Change Without Notice Freescale Semiconductor
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Electrical characteristics
3.5
No. 1 2 3
Electromagnetic Interference (EMI) characteristics
Table 12. EMI testing specifications1
Symbol Parameter SR Scan range SR Operating frequency VDD_LV_REGCOR LV operating voltages VDD_LV_CORx SR VDD_LV_PLL VDD_HV_REG VDD_HV_AD1 VDD_HV_AD0 VDD_HV_FL VDD_HV_OSC VDD_HV_IOx VDD_HV_REG VDD_HV_AD1 VDD_HV_AD0 VDD_HV_FL VDD_HV_OSC VDD_HV_IOx VDD_HV_REG VDD_HV_AD1 VDD_HV_AD0 VDD_HV_FL VDD_HV_OSC VDD_HV_IOx VDD_HV_REG VDD_HV_AD1 VDD_HV_AD0 VDD_HV_FL VDD_HV_OSC VDD_HV_IOx TA HV operating voltages SR -- -- 3.3 -- V Conditions -- -- -- Min 0.15 -- -- Typ -- -- 1.2 Max 1000 120 -- Unit MHz MHz V
4
Maximum amplitude SR
5
Device settings chosen for worst-case emissions from typical use configuration2
--
--
TBD
dBV
Maximum amplitude SR
No PLL frequency modulation -- -- TBD dBV
6
Maximum amplitude SR
2% PLL frequency modulation
-- -- TBD dBV
7
8
SR
Operating temperature
--
-40
--
125
C
NOTES: 1 EMI testing and I/O port waveforms per SAE J1752/3 issued 1995-03 and IEC 61967-1, 2. 2 Design target only, subject to change after silicon characterization.
3.6
Electrostatic discharge (ESD) characteristics
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts x (n + 1) supply pin). This test conforms to the AEC-Q100-002/-003/-011 standard.
MPC5643L Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 63
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Electrical characteristics
Table 13. ESD ratings1, 2
No. 1 2 Symbol VESD(HBM) VESD(MM) VESD(CDM) SR SR Parameter Electrostatic discharge (Human Body Model) Electrostatic discharge (Machine Model) Conditions TA = 25 C conforming to AEC-Q100-002 TA = 25 C conforming to AEC-Q100-003 Class H1C M2 Max value3 2000 200 500 C3A 750 (corners) V Unit V V
3
Electrostatic discharge TA = 25 C SR (Charged Device Model) conforming to AEC-Q100-011
NOTES: 1 All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2 A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. 3 Data based on characterization results, not tested in production.
3.7
* *
Static latch-up (LU)
A supply overvoltage is applied to each power supply pin. A current injection is applied to each input, output and configurable I/O pin. Table 14. Latch-up results
No. 1 Symbol LU SR Parameter Static latch-up class Conditions TA = 125 C conforming to JESD 78 Class II level A
Two complementary static tests are required on six parts to assess the latch-up performance:
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
3.8
* * * * * * * * * *
Voltage regulator electrical characteristics
High power regulator HPREG1 (internal ballast to support core current) High power regulator HPREG2 (external NPN to support core current) Low voltage detector (LVD_MAIN_1) for 3.3 V supply to IO (VDDIO) Low voltage detector (LVD_MAIN_2) for 3.3 V supply (VDDREG) Low voltage detector (LVD_MAIN_3) for 3.3 V flash supply (VDDFLASH) Low voltage detector (LVD_DIG_MAIN) for 1.2 V digital core supply (HPVDD) Low voltage detector (LVD_DIG_BKUP) for the self-test of LVD_DIG_MAIN High voltage detector (HVD_DIG_MAIN) for 1.2 V digital CORE supply (HPVDD) High voltage detector (HVD_DIG_BKUP) for the self-test of HVD_DIG_MAIN. Power on Reset (POR)
The voltage regulator is composed of the following blocks:
HPREG1 uses an internal ballast to support the core current. HPREG2 is used only when external NPN transistor is present on board to supply core current. The MPC5643L always powers up using HPREG1 if an external NPN transistor is present. Then the MPC5643L makes a transition from HPREG1 to HPREG2. This transition is dynamic. Once HPREG2 is fully operational, the controller part of HPREG1 is switched off. The supported bipolar transistor is a BCP68 from ON Semiconductor.
MPC5643L Microcontroller Data Sheet, Rev. 3 64 Preliminary--Subject to Change Without Notice Freescale Semiconductor
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Electrical characteristics
Table 15. HPREG1, HPREG2, Main LVDs, Digital HVD, and Digital LVD electrical specifications
No. Symbol Parameter External decoupling/ stability capacitor Combined ESR of external capacitor Number of pins for external decoupling/ stability capacitor Total capacitance on 1.2 V pins Start-up time after main supply stabilization Main high voltage detectors upper threshold Main high voltage detectors lower threshold Digital high voltage detector upper threshold Digital high voltage detector upper threshold Digital high voltage detector lower threshold Digital low voltage detector lower threshold POR rising/ falling supply threshold voltage SR Supply ramp time Conditions Min, max values shall be granted with respect to tolerance, voltage, temperature, and aging variations. -- Min Typ Max Units
1
SR
12
--
40
F
2
SR
0.03
--
0.5
3
SR
-- Ceramic capacitors, taking into account tolerance, aging, voltage and temperature variation Cload = 10 F x 4 -- -- Before a destructive reset initialization phase completion After a destructive reset initialization phase completion Before a destructive reset initialization phase completion -- -- --
5
--
--
--
4
CV1V2
SR
--
--
300
nF
5 6 7 8 9 10 11 12 13
tSU
-- -- 2.6
-- -- -- --
2.5 2.9 -- 1.5 1.4 1.4 1.110 2.6 3
ms V V V V V V V V/s
1.32 1.330 1.080 1.6 0.5 x 106
-- -- -- -- --
MPC5643L Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 65
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Electrical characteristics
VDD
BCRTL
BCP68 V1V2 ring on board
Rb Rs Cint
Lb ESR Cv1v2 Cext
V1V2 pin MPC5643L
Figure 4. BCP68 Board schematic example
NOTE
The combined ESR of the capacitors used on 1.2 V pins (V1V2 in the picture) shall be in the range of 30 m to 150 m. The minimum value of the ESR is constrained by the resonance caused by the external components, bonding inductance, and internal decoupling. The minimum ESR is required to avoid the resonance and make the regulator stable.
3.9
DC electrical characteristics
Table 16. DC electrical characteristics1
Symbol VIL VIL VIH VIH VHYS VOL_S D P P D T P Parameter Minimum low level input voltage Maximum level input voltage Minimum high level input voltage Maximum high level input voltage Schmitt trigger hysteresis Slow, low level output voltage Conditions -- -- -- -- -- IOL = 1.5 mA Min -0.12 -- 0.65 VDD_HV_IOx -- 0.1 VDD_HV_IOx -- Max -- 0.35 VDD_HV_IOx -- VDD_HV_IOx + 0.1
2
Table 16 gives the DC electrical characteristics at 3.3 V (3.0 V < VDD_HV_IOx < 3.6 V).
Unit V V V V V V
-- 0.5
MPC5643L Microcontroller Data Sheet, Rev. 3 66 Preliminary--Subject to Change Without Notice Freescale Semiconductor
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Electrical characteristics
Table 16. DC electrical characteristics1 (continued)
Symbol VOH_S VOL_M VOH_M VOL_F VOH_F VOL_SYM VOH_SYM IINJ IPU P P P P P P P P P Equivalent pull-down current IPD IIL IIL VILR VIHR VHYSR VOLR IPD P Input leakage current (all bidirectional ports) Input leakage current (all ADC input-only ports) RESET, low level input voltage RESET, high level input voltage RESET, Schmitt trigger hysteresis RESET, low level output voltage RESET, equivalent pull-down current D Parameter Slow, high level output voltage Medium, low level output voltage Medium, high level output voltage Fast, high level output voltage Fast, high level output voltage Symmetric, high level output voltage Symmetric, high level output voltage DC injection current per pin Equivalent pull-up current Conditions Min Max -- 0.5 -- 0.5 -- 0.5 -- 1 -- A -- 10 -- -- -- -0.12 0.65 VDD_HV_IOx 0.1 VDD_HV_IOx -- 10 -- -10 -- A 130 1 A 0.5 A 0.35 VDD_HV_IOx VDD_HV_IOx+0.12 -- 0.5 -- A 130 A A V V V V Unit V V V V V V V mA
IOH = -1.5 mA VDD_HV_IOx - 0.8 IOL = 2 mA IOH = -2 mA IOL = 1.5 mA -- VDD_HV_IOx - 0.8 --
IOH = -1.5 mA VDD_HV_IOx - 0.8 IOL = 1.5 mA --
IOH = -1.5 mA VDD_HV_IOx - 0.8 -- VIN = VIL VIN = VIH VIN = VIL VIN = VIH -1 -130
P P P P D D
TJ = -40 to +150 C TJ = -40 to +150 C -- -- -- IOL = 2 mA VIN = VIL VIN = VIH
NOTES: 1 These specifications are design targets and subject to change per device characterization. 2 "SR" parameter values must not exceed the absolute maximum ratings shown in Table 8.
3.10
Temperature sensor electrical characteristics
Table 17. Temperature sensor electrical characteristics
Symbol Accuracy -- TS P D Minimum sampling period Parameter Conditions TJ = -40 C to TA = 25 C TJ = TA to 125 C -- Min -10 -7 4 Max 10 7 -- Unit C C s
MPC5643L Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 67
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Electrical characteristics
3.11
Main oscillator electrical characteristics
Figure 5. Crystal oscillator and resonator connection scheme
The device provides an oscillator/resonator driver. Figure 5 describes a simple model of the internal oscillator driver and provides an example of a connection for an oscillator or a resonator.
EXTAL CL Crystal EXTAL RP
XTAL
DEVICE
VDD
CL
I
R EXTAL Resonator
XTAL
DEVICE
XTAL
DEVICE
NOTE
XTAL/EXTAL must not be directly used to drive external circuits. Figure 6. Main oscillator electrical characteristics
VDD VDDMIN
VXTAL VXOSCHS 90% VXOSCHSOP 10% TXOSCHSSU valid internal clock
1/fXOSCHS
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Electrical characteristics
x
Table 18. Main oscillator electrical characteristics
Symbol fXOSCHS Parameter SR Oscillator frequency Oscillator transconductance gmXOSCHS VXOSCHS VXOSCHSOP IXOSCHS P Oscillation amplitude D Oscillation operating point Conditions1 Min -- VDD = 3.3 V 10% fOSC = 4, 8, 10, 12, 16 MHz fOSC = 40 MHz D -- -- fOSC = 4, 8, 10, 12 MHz, OSCILLATOR_MARGIN = 0 fOSC = 16, 40 MHz, OSCILLATOR_MARGIN = 1 SR SR Input high level CMOS Schmitt Trigger Input low level CMOS Schmitt Trigger Oscillator bypass mode Oscillator bypass mode 4.0 4.5 1.3 1.1 -- -- -- -- 0.65 x VDD -0.4 Value Unit Typ -- -- -- -- 0.82 -- -- -- -- -- Max 40.0 11 -- -- -- 3.5 6 ms 2 VDD + 0.4 0.35 x VDD V V V mA mA/V V MHz
D Oscillator consumption Oscillator start-up time
TXOSCHSSU
T
VIH VIL
NOTES: 1V DD = 3.3 V 10%, TJ = -40 to +150 C, unless otherwise specified.
3.12
FMPLL electrical characteristics
Table 19. FMPLL electrical characteristics
Symbol Parameter Conditions Min 4 4 4 20 16 -- 1.6 24 -- Stable oscillator (fPLLIN = 4 MHz), stable VDD 20 -- Typ -- -- -- -- -- -- -- -- -- -- Max 40 16 1202 150 120 1 / fsys 3.7 MHz Upper limit 56 TBD 200 MHz s Unit MHz MHz MHz MHz MHz ns
PLL reference frequency range1 Crystal reference fREF_CRYSTAL D fREF_EXT fPLL_IN D Phase detector input frequency range (after pre-divider) Clock frequency range in normal mode Free running frequency -- -- Measured using clock division (typically /16) -- -- Lower limit
fFMPLLOUT D fFREE fsys tCYC fLORL fLORH fSCM tLOCK P
D On-chip PLL frequency2 D System clock period Loss of reference frequency D window3 D Self-clocked mode frequency4,5 P Lock time
MPC5643L Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 69
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Electrical characteristics
Table 19. FMPLL electrical characteristics (continued)
Symbol tlpll tdc Parameter D PLL lock time 6, 7 D Duty cycle of reference CLKOUT period jitter CJITTER T Long-term jitter (avg. over 2 ms interval), fSYS maximum -6 -- -- -6 -18 0.25 -0.5 -- -- -- -- -- -- -- -- -- -- 6 500 6 6 18 4.012 -8.0 100
8,9,10,11
Conditions -- -- Peak-to-peak (clock edge to clock edge), fSYS maximum
Min -- 40 TBD
Typ -- -- --
Max 200 60 TBD
Unit s % % fCLK
OUT
ns ps ns % fsys % fsys % fsys kHz
tPKJIT tLTJIT
fLCK fUL fCS fDS fMOD
T T D D
Single period jitter (peak to peak) PHI @ 16 MHz, Input clock @ 4 MHz Long term jitter Frequency LOCK range Frequency un-LOCK range Modulation Depth Center spread Down Spread PHI @ 16 MHz, Input clock @ 4 MHz -- --
D D Modulation frequency13
NOTES: 1 Considering operation with PLL not bypassed. 2 With FM, +2% maximum. 3 "Loss of Reference Frequency" window is the reference frequency range outside of which the PLL is in self clocked mode. 4 Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside the fLOR window. 5f VCO self clock range is 20-150 MHz. fSCM represents fSYS after PLL output divider (ERFD) of 2 through 16 in enhanced mode. 6 This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for this PLL, load capacitors should not exceed these limits. 7 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the synthesizer control register (SYNCR). 8 This value is determined by the crystal manufacturer and board design. 9 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fSYS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the CJITTER percentage for a given interval. 10 Proper PC board layout procedures must be followed to achieve specifications. 11 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of CJITTER and either fCS or fDS (depending on whether center spread or down spread modulation is enabled). 12 This value is true when operating at frequencies above 60 MHz, otherwise fCS is 2% (above 64 MHz). 13 Modulation depth is attenuated from depth setting when operating at modulation frequencies above 50kHz.
MPC5643L Microcontroller Data Sheet, Rev. 3 70 Preliminary--Subject to Change Without Notice Freescale Semiconductor
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Electrical characteristics
3.13
16 MHz RC oscillator electrical characteristics
Table 20. RC oscillator electrical characteristics
Symbol fRC Parameter P RC oscillator frequency P P Fast internal RC oscillator variation with respect to fRC. Post trim accuracy: The variation of the TJ = 25 C PTF1 from the 16 MHz clock Conditions TJ = 25 C -- Min -- -- -- Typ 16 -- -- Max -- 5 1 Unit MHz % %
RCMVAR RCMTRIM
NOTES: 1 PTF = Post Trimming Frequency: The frequency of the output clock after trimming at typical supply voltage and temperature.
MPC5643L Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 71
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Electrical characteristics
3.14
ADC electrical characteristics
Offset Error OSE 1023 Gain Error GE
The device provides a 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter.
1022 1021
1020 1019 1 LSB ideal = VDD_ADC / 1024 1018 (2)
code out 7 (1) 6 5 (5) 4 (4) 3 (3) (1) Example of an actual transfer curve (2) The ideal transfer curve (3) Differential non-linearity error (DNL) (4) Integral non-linearity error (INL) (5) Center of a step of the actual transfer curve
2 1
1 LSB (ideal)
0 1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023 Vin(A) (LSBideal)
Offset Error OSE
Figure 21. ADC Characteristics and Error Definitions
3.14.1
Input Impedance and ADC Accuracy
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; further, it sources charge during the sampling phase, when the analog signal source is a high-impedance source. A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to
MPC5643L Microcontroller Data Sheet, Rev. 3 72 Preliminary--Subject to Change Without Notice Freescale Semiconductor
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Electrical characteristics
be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the ADC itself. In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: CS being substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path to ground. For instance, assuming a conversion rate of 1 MHz, with CS equal to 3 pF, a resistance of 330 k is obtained (REQ = 1 / (fC x CS), where fC represents the conversion rate at the considered channel). To minimize the error induced by the voltage partitioning between this resistance (sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external circuit must be designed to respect the Equation 7: R S + R F + R L + R SW + R AD -1 V A * -------------------------------------------------------------------------- < -- LSB R EQ 2
Eqn. 7
Equation 7 generates a constraint for external network design, in particular on resistive path. Internal switch resistances (RSW and RAD) can be neglected with respect to external resistances.
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME VDD Channel Selection RSW1
Sampling
Source RS
Filter RF
Current Limiter RL
RAD
VA
CF
CP1
CP2
RS Source Impedance RF Filter Resistance CF Filter Capacitance Current Limiter Resistance RL RSW1 Channel Selection Switch Impedance RAD Sampling Switch Impedance CP Pin Capacitance (two contributions, CP1 and CP2) CS Sampling Capacitance
Figure 22. Input Equivalent Circuit A second aspect involving the capacitance network shall be considered. Assuming the three capacitances CF, CP1 and CP2 are initially charged at the source voltage VA (refer to the equivalent circuit reported in Figure 22): A charge sharing phenomenon is installed when the sampling phase is started (A/D switch close).
MPC5643L Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 73
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Electrical characteristics Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
VCS VA VA2
Voltage Transient on CS V < 0.5 LSB
1 2
1 < (RSW + RAD) CS << TS
VA1
2 = RL (CS + CP1 + CP2)
TS t
Figure 23. Transient Behavior during Sampling Phase In particular two different transient periods can be distinguished: * A first and quick charge transfer from the internal capacitance CP1 and CP2 to the sampling capacitance CS occurs (CS is supposed initially completely discharged): considering a worst case (since the time constant in reality would be faster) in which CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitances CP and CS are in series, and the time constant is CP * CS 1 = ( R SW + R AD ) * -------------------CP + CS
Eqn. 8
Equation 8 can again be simplified considering only CS as an additional worst condition. In reality, the transient is faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time TS is always much longer than the internal time constant:
1 < ( R SW + R AD ) * C S T S Eqn. 9
The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the voltage VA1 on the capacitance according to Equation 10:
V A1 * ( C S + C P1 + C P2 ) = V A * ( C P1 + C P2 ) * Eqn. 10
A second charge transfer involves also CF (that is typically bigger than the on-chip capacitance) through the resistance RL: again considering the worst case in which CP2 and CS were in parallel to CP1 (since the time constant in reality would be faster), the time constant is: 2 < R L * ( C S + C P1 + C P2 ) Eqn. 11
In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time TS, a constraints on RL sizing is obtained:
MPC5643L Microcontroller Data Sheet, Rev. 3 74 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical characteristics
10 * 2 = 10 * R L * ( C S + C P1 + C P2 ) < TS
Eqn. 12
Of course, RL shall be sized also according to the current limitation constraints, in combination with RS (source impedance) and RF (filter resistance). Being CF definitively bigger than CP1, CP2 and CS, then the final voltage VA2 (at the end of the charge transfer transient) will be much higher than VA1. Equation 13 must be respected (charge balance assuming now CS already charged at VA1):
VA2 * ( C S + C P1 + C P2 + C F ) = V A * C F + V A1 * ( C P1 + C P2 + C S ) Eqn. 13
The two transients above are not influenced by the voltage source that, due to the presence of the RFCF filter, is not able to provide the extra charge to compensate the voltage drop on CS with respect to the ideal source VA; the time constant RFCF of the filter is very high with respect to the sampling time (TS). The filter is typically designed to act as anti-aliasing.
Analog Source Bandwidth (VA) Noise
TC 2 RFCF (Conversion Rate vs. Filter Pole) fF = f0 (Anti-aliasing Filtering Condition) 2 f0 fC (Nyquist)
f0
f
Sampled Signal Spectrum (fC = conversion Rate)
Anti-Aliasing Filter (fF = RC Filter pole)
fF
f
f0
fC
f
Figure 24. Spectral Representation of Input Signal Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, fF), according to the Nyquist theorem the conversion rate fC must be at least 2f0; it means that the constant time of the filter is greater than or at least equal to twice the conversion period (TC). Again the conversion period TC is longer than the sampling time TS, which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter RFCF is definitively much higher than the sampling time TS, so the charge level on CS cannot be modified by the analog signal source during the time in which the sampling switch is closed. The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage drop on CS; from the two charge balance equations above, it is simple to derive Equation 14 between the ideal and real sampled voltage on CS: Eqn. 14 VA C P1 + C P2 + C F ----------- = ------------------------------------------------------V A2 C P1 + C P2 + C F + C S
MPC5643L Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 75
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Electrical characteristics
From this formula, in the worst case (when VA is maximum, that is for instance 5 V), assuming to accept a maximum error of half a count, a constraint is evident on CF value: Eqn. 15 C F > 2048 * C S Table 25. ADC conversion characteristics (operating)
Symbol fCK fs Parameter Conditions1 -- -- TBD TBD time4 TBD -- -- -- VREF range = 4.5 to 5.5 V VREF range = 3.0 to 3.6 V -- Min Typ Max Unit 3 -- TBD -- -- 60 MHz
ADC Clock frequency (depends on ADC SR configuration) (The duty cycle depends on AD_CK2 frequency) SR Sampling frequency Sample time3
-- 1.00 MHz -- -- ns
tADC_S D tADC_C P Conversion CS5 CP1 CP2
5 5
-- TBD s -- s
0.625 -- -- -- -- -- -- --
D ADC input sampling capacitance D ADC input pin capacitance 1 D ADC input pin capacitance 2 Internal resistance of analog source
-- 7.32 pF -- TBD pF -- TBD pF -- -- -- 0.6 0.9 825 k k
RSW15 D RAD5
D Internal resistance of analog source Input current injection
IINJ
T
Current injection on one ADC input, different from the TBD converted one. Remains within TUE spec. -- -- -- -- -- -- -3 -1.0 -4 -- -6 TBD
-- TBD mA
INL DNL OFS GNE TUE TUE
P Integral non linearity P Differential non linearity T Offset error T Gain error P Total unadjusted error without current injection T Total unadjusted error with current injection
-- -- -- 1 --
3
LSB
1.0 LSB 4 -- 6 LSB LSB LSB
-- TBD LSB
NOTES: 1V DD = 3.3 V, TJ = -40 to +150 C, unless otherwise specified and analog input voltage from VAGND to VAREF. 2 AD_CK clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC. 3 During the sample time the input capacitance CS can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tADC_S. After the end of the sample time tADC_S, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tADC_S depend on programming. 4 This parameter does not include the sample time tADC_S, but only the time for determining the digital result and the time to load the result register with the conversion result. 5 See Figure 22.
MPC5643L Microcontroller Data Sheet, Rev. 3 76 Preliminary--Subject to Change Without Notice Freescale Semiconductor
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Electrical characteristics
3.15
No. 1 2 3 4 5 6 7
Flash memory electrical characteristics
Table 26. Flash program and erase electrical specifications
Symbol Parameter Min Typ1 -- -- -- -- -- -- -- 39 48 TBD TBD TBD TBD TBD Factory Initial Lifetime Unit Avg2 Max3 Max4 -- 53 TBD TBD TBD TBD TBD -- 100 500 750 900 1300 500 500 5000 5000 5000 7500 s s ms ms ms ms ms
TDWPROGRAM *5 Double word (64 bits) program time6 TPPROGRAM *5 Page(128 bits) program time6
5 5 5
T16KPPERASE * 16 KB block pre-program and erase time T48KPPERASE * 48 KB block pre-program and erase time T64KPPERASE * 64 KB block pre-program and erase time T128KPPERASE *5 128 KB block pre-program and erase time T256KPPERASE * 256 KB block pre-program and erase time
5
2600 15000
NOTES: 1 Typical program and erase times assume nominal supply values and operation at T = 25 C. These values are J characterized, but not tested. 2 Factory Average program and erase times represent the effective performance averaged over > 1024 pages or blocks, and are provided for factory throughput estimation assuming < 100 program/erase cycles, nominal supply values and operation at TJ = 25 C. These values are characterized, but not tested. 3 Initial Max program and erase times provide guidance for time-out limits used in the factory and apply for < 100 program/erase cycles, nominal supply values and operation at TJ = 25 C. These values are verified at production test. 4 Lifetime Max program and erase times apply across the voltage, temperature, and cycling range of product life. These values are characterized, but not tested. 5 See Notes for individual specifications, as shown in column headings. 6 Actual hardware programming times. These do not include software overhead.
Table 27. Flash module life
Value No. Symbol Parameter Min 1 2 P/E P/E C C Number of program/erase cycles per block for 16 KB, 48 KB, 100,000 and 64 KB blocks over the operating temperature range1 Number of program/erase cycles per block for 128 KB and 256 KB blocks over the operating temperature range1. 1,000 Typ -- 100,0002 (TBD) Max -- -- cycles cycles Unit
3
Minimum data retention at 85 C average ambient temperature3 Blocks with 0-1,000 P/E cycles Retention C Blocks with 1,001-10,000 P/E cycles Blocks with 10,001-100,000 P/E cycles
20 10 5
-- -- --
-- -- --
years
NOTES: 1 Operating temperature range is T from -40 C to 150 C. J Typical endurance is evaluated at 25 oC. Product qualification is performed to the minimum specification. For additional information on the Freescale definition of Typical Endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory. 2 Typical P/E cycles is 100,000 cycles for 128 KB and 256 KB blocks. For additional information on the Freescale definition of Typical Endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory. 3 Ambient temperature averaged over duration of application, not to exceed product operating temperature range.
MPC5643L Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 77
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Electrical characteristics Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
3.16
3.16.1
AC specifications
Pad AC specifications
Table 28. Pad AC specifications (3.3 V, IPP_HVE = 0)1
Tswitchon1 (ns) Min 3 3 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max 40 40 40 40 15 15 15 15 6 6 6 6 8 -- Rise/Fall2 (ns) Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max 40 50 75 100 12 25 40 70 4 7 12 18 5 TBD Frequency (MHz) Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max 4 2 2 2 40 20 13 7 72 55 40 25 50 -- Current slew3 (mA/ns) Min 0.01 0.01 0.01 0.01 2.5 2.5 2.5 2.5 3 7 7 7 3 -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max 2 2 2 2 7 7 7 7 40 40 40 40 25 -- 25 50 100 200 25 50 100 200 25 50 100 200 25 50 Load drive (pF)
No.
Pad
1
Slow
T 3 3 1 1
2
Medium
T 1 1 1 1
3
Fast
T 1 1
4 5
Symmetric Pull Up/Down (3.6 V max)
T D
1 --
NOTES: 1 Propagation delay from V DD_HV_IOx/2 of internal signal to Pchannel/Nchannel switch-on condition. 2 Slope at rising/falling edge. 3 Data based on characterization results, not tested in production.
MPC5643L Microcontroller Data Sheet, Rev. 3 78 Preliminary--Subject to Change Without Notice Freescale Semiconductor
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VDDE/2 Pad Data Input
Rising Edge Output Delay
Falling Edge Output Delay VOH
Pad Output
VOL
Figure 16. Pad output delay
3.17
3.17.1
AC timing characteristics
RESET pin characteristics
VDD VDDMIN
The MPC5643L implements a dedicated bidirectional RESET pin.
nRSTIN
VIH VIL device reset forced by nRSTIN device start-up phase
Figure 29. Start-up reset requirements
MPC5643L Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice
Electrical characteristics
VRSTIN hw_rst
VDD
`1'
VIH
VIL
`0'
filtered by hysteresis filtered by lowpass filter WFRST filtered by lowpass filter WFRST WNFRST unknown reset state device under hardware reset
Figure 30. Noise filtering on reset signal Table 31. RESET electrical characteristics
No. Symbol Parameter Output transition time output pin2 1 Ttr D Conditions1 CL = 25pF CL = 50pF CL = 100pF 2 3 WFRST P nRSTIN input filtered pulse -- -- Min -- -- -- -- 500 Typ -- -- -- -- -- Max 12 25 40 40 -- ns ns ns Unit
WNFRST P nRSTIN input not filtered pulse
NOTES: 1V DD = 3.3 V 10%, TJ = -40 to +150 C, unless otherwise specified 2 C includes device and package capacitance (C L PKG < 5 pF).
3.17.2
No. 1 2 3 4 5 6 7
IEEE 1149.1 interface timing
Table 32. JTAG pin AC electrical characteristics
Symbol tJCYC tJDC tTCKRISE tTMSS, tTDIS D TCK cycle time D TCK clock pulse width (measured at VDDE/2) D TCK rise and fall times (40%-70%) D TMS, TDI data setup time Parameter Conditions -- -- -- -- -- -- -- Min Max Unit 100 40 -- 5 25 -- 0 -- 60 3 -- -- 20 -- ns ns ns ns ns ns ns
tTMSH, tTDIH D TMS, TDI data hold time tTDOV tTDOI D TCK low to TDO data valid D TCK low to TDO data invalid
MPC5643L Microcontroller Data Sheet, Rev. 3 80 Preliminary--Subject to Change Without Notice Freescale Semiconductor
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Electrical characteristics
Table 32. JTAG pin AC electrical characteristics (continued)
No. 8 11 12 13 14 15 Symbol tTDOHZ tBSDV tBSDVZ tBSDHZ tBSDST tBSDHT Parameter D TCK low to TDO high impedance D TCK falling edge to output valid D TCK falling edge to output valid out of high impedance D TCK falling edge to output high impedance D Boundary scan input valid to TCK rising edge D TCK rising edge to boundary scan input invalid Conditions -- -- -- -- -- -- Min Max Unit -- -- -- -- 50 50 20 50 50 50 -- -- ns ns ns ns ns ns
TCK 2 3 1 3 2
Figure 17. JTAG test clock input timing
TCK
4 5
TMS, TDI
6 7 8
TDO
Figure 18. JTAG test access port timing
MPC5643L Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 81
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Electrical characteristics Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
TCK 11 13
Output Signals
12
Output Signals 14 15
Input Signals
Figure 19. JTAG boundary scan timing
3.17.3
No. 1 2 3 4 5 6 7 8 9 10
Nexus timing
Table 33. Nexus debug port timing1
Symbol tMCYC tMDC tMDOV tEVTIPW tEVTOPW tTCYC tTDC tNTDIH, tNTMSH tJOV D MCKO Cycle Time D MCKO Duty Cycle D MCKO Low to MDO, MSEO, EVTO Data D EVTI Pulse Width D EVTO Pulse Width D TCK Cycle Time3 Valid2 Parameter Conditions Min -- -- -- -- -- -- -- -- 15.6 40 -0.1 4.0 1 40 40 8 5 0 -- 60 -- -- 25 Max -- 60 Unit ns %
0.25 tMCYC -- tTCYC tMCYC ns % ns ns ns
D TCK Duty Cycle
tNTDIS, tNTMSS D TDI, TMS Data Setup Time D TDI, TMS Data Hold Time
D TCK Low to TDO Data Valid
MPC5643L Microcontroller Data Sheet, Rev. 3 82 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical characteristics NOTES: 1 JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. 2 MDO, MSEO, and EVTO data is held valid until next MCKO low cycle. 3 The system clock frequency needs to be three times faster than the TCK frequency. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages 83
1 2 MCKO
3
MDO MSEO EVTO Output Data Valid
5
EVTI
4
Figure 20. Nexus output timing
MPC5643L Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice
Electrical characteristics Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
6
7
TCK
8 9
TMS, TDI
10
TDO
Figure 21. Nexus TDI, TMS, TDO timing
3.17.4
No. 1 2 3
External interrupt timing (IRQ pin)
Table 34. External interrupt timing
Symbol tIPWL tIPWH tICYC Parameter D IRQ pulse width low D IRQ pulse width high D IRQ edge to edge time1 Conditions -- -- -- Min Max Unit 3 3 6 -- -- -- tCYC tCYC tCYC
NOTES: 1 Applies when IRQ pins are configured for rising edge or falling edge events, but not both.
MPC5643L Microcontroller Data Sheet, Rev. 3 84 Preliminary--Subject to Change Without Notice Freescale Semiconductor
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CLKOUT
IRQ
1 2 3
Figure 22. External interrupt timing
3.17.5
No. 1 2
FlexCAN timing
Table 35. FlexCAN timing
Symbol tCANOV tCANSU Parameter CTNX output valid after CLKOUT rising edge (output delay) CNRX input valid to CLKOUT rising edge (setup time) Conditions -- -- Min -- -- Max 26.0 9.8 Unit ns ns
3.17.6
No.
DSPI timing
Table 36. DSPI timing
Symbol D Parameter DSPI cycle time Conditions Master (MTFE = 0) Slave (MTFE = 0) Slave Receive Only Mode1 PCS to SCK delay After SCK delay SCK duty cycle Slave access time Slave SOUT disable time -- -- -- SS active to SOUT valid SS inactive to SOUT High-Z or invalid Min 62 62 16 16 16 Max -- -- -- -- -- ns ns ns Unit
1
tSCK
D D
2 3 4 5 6
tCSC tASC tSDC tA tDIS
D D D D D
0.4 x tSCK 0.6 x tSCK ns -- -- 40 10 ns ns
MPC5643L Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice
Electrical characteristics
Table 36. DSPI timing (continued)
No. 7 8 Symbol tPCSC tPASC D D Parameter PCSx to PCSS time PCSS to PCSx time Data setup time for inputs 9 tSUI D Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) Data hold time for inputs 10 tHI D Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) Data valid (after SCK edge) 11 tSUO D Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) Data hold time for outputs 12 tHO D Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) 13 fmax D Maximum DSPI speed -- 6 -2 -- -- -- 4 MH z Master (MTFE = 0) Slave -- -- -2 6 12 4 -- -- ns Master (MTFE = 0) Slave 11 -5 -- -- -- -- 4 23 ns Master (MTFE = 0) Slave 5 20 -5 4 -- -- -- -- ns Conditions -- -- Master (MTFE = 0) Slave Min 13 13 20 2 Max -- -- -- -- ns Unit ns ns
NOTES: 1 Slave Receive Only Mode can operate at a maximum frequency of 60 MHz. Note that in this mode, the DSPI can receive data on SIN, but no valid data is transmitted on SOUT.
MPC5643L Microcontroller Data Sheet, Rev. 3 86 Preliminary--Subject to Change Without Notice Freescale Semiconductor
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Electrical characteristics Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages 87
2 PCSx 4 SCK Output (CPOL=0) 4 1
3
SCK Output (CPOL=1) 9 SIN 10 Data 12 SOUT First Data Data Last Data 11 Last Data
First Data
Figure 23. DSPI classic SPI timing -- master, CPHA = 0
PCSx
SCK Output (CPOL=0) 10 SCK Output (CPOL=1) 9 SIN First Data 12 SOUT First Data Data Data Last Data 11 Last Data
Figure 24. DSPI classic SPI timing -- master, CPHA = 1
MPC5643L Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice
Electrical characteristics Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages Freescale Semiconductor
2 SS 1 SCK Input (CPOL=0) 4 SCK Input (CPOL=1) 5 SOUT First Data 9 SIN 10 Data 12 Data 11 4
3
6
Last Data
First Data
Last Data
Figure 25. DSPI classic SPI timing -- slave, CPHA = 0
SS
SCK Input (CPOL=0)
SCK Input (CPOL=1) 5 SOUT
11 12 First Data 9 10 Data Last Data Data Last Data 6
SIN
First Data
Figure 26. DSPI classic SPI timing -- slave, CPHA = 1
MPC5643L Microcontroller Data Sheet, Rev. 3 88 Preliminary--Subject to Change Without Notice
Electrical characteristics Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages 89
3 PCSx 4 2 SCK Output (CPOL=0) SCK Output (CPOL=1) 9 SIN First Data 12 SOUT First Data Data Data 11 Last Data Last Data 4 1
10
Figure 27. DSPI modified transfer format timing -- master, CPHA = 0
PCSx
SCK Output (CPOL=0)
SCK Output (CPOL=1) 9 SIN First Data Data 12 SOUT First Data Data 10
Last Data 11 Last Data
Figure 28. DSPI modified transfer format timing -- master, CPHA = 1
MPC5643L Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice
Electrical characteristics 3 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
SS
2 1
SCK Input (CPOL=0) 4 SCK Input (CPOL=1) 5 SOUT First Data 9 SIN First Data Data Data 11 12 Last Data 10 Last Data 6 4
Figure 29. DSPI modified transfer format timing - slave, CPHA = 0
SS
SCK Input (CPOL=0)
SCK Input (CPOL=1) 5 SOUT
11 12 First Data 9 10 Data Last Data Data Last Data 6
SIN
First Data
Figure 30. DSPI modified transfer format timing -- slave, CPHA = 1
MPC5643L Microcontroller Data Sheet, Rev. 3 90 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Freescale Semiconductor PCSS PCSx 7
Figure 31. DSPI PCS strobe (PCSS) timing
MPC5643L Microcontroller Data Sheet, Rev. 3
Preliminary--Subject to Change Without Notice
8 Electrical characteristics
91
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92
4 Package characteristics
4.1 Package mechanical data
Package characteristics
MPC5643L Microcontroller Data Sheet, Rev. 3
Figure 32. 144 LQFP package mechanical drawing (1 of 2)
Preliminary--Subject to Change Without Notice
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Freescale Semiconductor Package characteristics
MPC5643L Microcontroller Data Sheet, Rev. 3
Figure 33. 144 LQFP package mechanical drawing (2 of 2)
Preliminary--Subject to Change Without Notice
93
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94
Package characteristics
MPC5643L Microcontroller Data Sheet, Rev. 3
Figure 34. 257 MAPBGA package mechanical drawing (1 of 2)
Preliminary--Subject to Change Without Notice
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Freescale Semiconductor Package characteristics
MPC5643L Microcontroller Data Sheet, Rev. 3
Figure 35. 257 MAPBGA package mechanical drawing (2 of 2)
Preliminary--Subject to Change Without Notice
95
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Ordering information
5
Ordering information
M PC 5643L F F0 M LQ 1
Qualification status Core code (Power Architecture) Device number F = FlexRay (blank) = No FlexRay Fab and mask identifier Temperature range Package identifier Operating frequency Tape and reel status Temperature range M = -40 C to 125 C V = -40 C to 105 C Package identifier LQ = 144 LQFP MM = 257 MAPBGA Operating frequency 1 = 120 MHz 8 = 80 MHz Tape and reel status R = Tape and reel (blank) = Trays Qualification status P = Pre-qualification M = Fully spec. qualified, general market flow S = Fully spec. qualified, automotive flow
R
Note: Not all options are available on all devices. Refer to Table 37.
Table 37. Orderable part number summary
Part number1 PPC5643LFF0MLQ1 PPC5643LFF0MMM1 PPC5643LF0MLQ1 PPC5643LF0MMM1 PPC5643LFF0VLQ1 PPC5643LFF0VMM1 PPC5643LF0VLQ1 PPC5643LF0VMM1 PPC5643LFF0MLQ8 PPC5643LFF0MMM8 Flash/SRAM 1 MB/128 KB 1 MB/128 KB 1 MB/128 KB 1 MB/128 KB 1 MB/128 KB 1 MB/128 KB 1 MB/128 KB 1 MB/128 KB 1 MB/128 KB 1 MB/128 KB Package 144 LQFP (Pb free) 257 MAPBGA (Pb free) 144 LQFP (Pb free) 257 MAPBGA (Pb free) 144 LQFP (Pb free) 257 MAPBGA (Pb free) 144 LQFP (Pb free) 257 MAPBGA (Pb free) 144 LQFP (Pb free) 257 MAPBGA (Pb free) Speed (MHz) 120 120 120 120 120 120 120 120 80 80 Other features FlexRay -40-125 C FlexRay -40-125 C No FlexRay -40-125 C No FlexRay -40-125 C FlexRay -40-105 C FlexRay -40-105 C No FlexRay -40-105 C No FlexRay -40-105 C FlexRay -40-125 C FlexRay -40-125 C
MPC5643L Microcontroller Data Sheet, Rev. 3 96 Preliminary--Subject to Change Without Notice Freescale Semiconductor
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Document revision history
Table 37. Orderable part number summary (continued)
Part number1 PPC5643LF0MLQ8 PPC5643LF0MMM8 PPC5643LFF0VLQ8 PPC5643LFF0VMM8 PPC5643LF0VLQ8 PPC5643LF0VMM8 Flash/SRAM 1 MB/128 KB 1 MB/128 KB 1 MB/128 KB 1 MB/128 KB 1 MB/128 KB 1 MB/128 KB Package 144 LQFP (Pb free) 257 MAPBGA (Pb free) 144 LQFP (Pb free) 257 MAPBGA (Pb free) 144 LQFP (Pb free) 257 MAPBGA (Pb free) Speed (MHz) 80 80 80 80 80 80 Other features No FlexRay -40-125 C No FlexRay -40-125 C FlexRay -40-105 C FlexRay -40-105 C No FlexRay -40-105 C No FlexRay -40-105 C
NOTES: 1 All packaged devices are PPC, rather than MPC or SPC, until product qualifications are complete. The unpackaged device prefix is PCC, rather than SCC, until product qualification is complete. Not all configurations are available in the PPC parts.
6
Document revision history
Table 38. Revision history
Revision 1 2 Date 2 Mar 2009 5 May 2009 Initial release. Updated, Advance Information. --Revised SINAD/SNR specifications. -- Updated pinout and pin multiplexing information. Updated, Advance Information, Public release. -- Throughout this document, added information for 257 MAPBGA package. -- Updated Table 1, MPC5643L device summary. -- Updated Section 1.3, Feature Details. -- Updated pin-out and pin multiplexing tables. -- In Section 3, Electrical characteristics, added symbols for signal characterization methods. -- In Table 8, updated maximum ratings. -- In Table 10 and Table 11, removed moving-air thermal characteristics. -- Updated Section 3.8, Voltage regulator electrical characteristics. -- Updated Section 3.14, ADC electrical characteristics. -- Updated Section 3.15, Flash memory electrical characteristics. -- Updated Section 3.17.1, RESET pin characteristics. -- Removed External interrupt timing (IRQ pin) timing specifications. -- Updated Section 3.17.6, DSPI timing. -- Updated Section 5, Ordering information. Description of Changes
Table 38 summarizes revisions to this document.
3
5 Oct 2009
MPC5643L Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 97
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
Document revision history Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5643L products in 257 MAPBGA packages
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Rev. 3 10/2009 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc. 2009. All rights reserved.
MPC5643L Microcontroller Data Sheet, Rev. 3 98 Preliminary--Subject to Change Without Notice Freescale Semiconductor

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